Abstract: A method for use with digital automated test equipment for measuring an asynchronous analog frequency, which analog frequency may be up to at least four times the operational frequency of the digital automated test equipment. From test vectors related to the frequency of interest known to represent good components, a pattern of test vectors with randomly assigned timing sets is created. Then, the maximum number of counts and the period increment is set. The selected pattern of test vectors are then applied to the unit under test and the received waveforms compared to the stored patterns. If there is no match, the period of the timing sets within the frequency range of interest is adjusted by a predetermined increment, and the test is repeated until there is a match. Since the period is now known, the frequency of the asynchronous analog signal can be calculated.

Abstract: The invention relates to a circuit architecture for easily carrying out tests on a non-volatile memory device having at least one matrix (2) of memory cells. The architecture is distinctive in that it comprises a bi-directional internal data bus (3) extending from one end to the other of the memory device, a plurality of signal sources (8) inside said memory device, at least one local bus (6) connected to the data bus (3), and timing means (10) for timing the access of the local bus (6) to the data bus (3) and the selective access of the signal sources (8) to the local bus (6) during the same test cycle.

Abstract: A design of logic circuitry to be tested is divided into one or more discrete logic modules usable in other designs of circuitry. An automated test pattern generator (ATPG) program and its tools are applied to the discrete module while not also being applied to the remainder of the logic circuitry, with the result that an ATPG pattern is provided for the module. When the module is reused in another design of logic circuitry, the ATPG pattern is also reusable in such other design.

Abstract: A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns, and a pair of complimentary digit lines being provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complimentary data lines. The data lines are coupled to respective inputs of a sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data is selectively coupled to the inputs of the sense amplifier from the complimentary digit lines for an addressed column. In a test mode, the multiplexer connects an I/O line for one array to one of the data lines and an I/O line for the other array to the other data line.

Abstract: A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

Abstract: An test circuit and method for testing an integrated device having an embedded function and a built-in test circuit for testing the embedded function. The built-in test circuit provides control signals to the embedded function based upon an internal state of the built-in test circuit. The integrated device is tested by comparing the control signals provided to the embedded function to the desired control signals based upon the internal state of the built-in self test circuit to confirm the proper operation of the built-in self test circuit. The internal state of the built-in test circuit is monitored and the control signals provided to the embedded function are monitored. The monitored signals are compared to an expected signal pattern based upon the monitored internal state of the built-in test circuit. An error signal is generated if the comparison determines that the monitored control signals do not correspond to the expected signal pattern.

Abstract: A system and method for testing of a memory during burn-in is disclosed. In one aspect, the method and system include an address generator. The address generator includes a shift register means. The shift register includes n bit positions. The n bit positions are for storing n bits. The n bits are capable of being in a plurality of patterns. The address generator further includes a counter coupled to the shift register means. The counter includes a value that is incremented in response to a particular pattern of the plurality of patterns. The address generator has a complement mechanism coupled to the shift register and the counter which provides a complement of at least a portion of the n bits stored in the n bit positions in response to the value in the counter. In another aspect, the method and system comprise the address generator previously discussed coupled to the memory undergoing testing.

Abstract: A fault tolerant computer system includes a number of lockstep subsystems, each of which comprises a parallel input signature generator, used for data compression to allow practical comparison of the operation of internal modules of the lockstep subsystem, and a logic analyzer which stores the outputs of the internal modules of the lockstep subsystem. A signature comparator is connected to receive the signatures from the signature generators of the individual lockstep subsystems. The signature comparator generates a trigger signal for triggering the logic analyzers on detecting a difference in the signatures. The logic analyzers store enough states to include the first difference from a module following a detected difference in the signature outputs. The logic analyzer traces are searched automatically after an out-of-sync event to locate the first difference in operation and to determine which internal module provided the faulty output and then that module is labelled as broken.

Abstract: A system software solution for testing various network elements/entities and processes in a telecommunications network is provided. A network under test contains network entities which save data to a common database that is associated with processing particular test cases. A server correlates database data from the network under test and compares it to anticipated test case results. A disposition of the test cases is determined. Various elements of the invention interface appropriately, and process accordingly, to accomplish the testing and test result(s) disposition. In addition, the test system provides a means to verify billing records within the telecommunications network.

Abstract: An intermediate value derived from old and new data record values or old and new data themselves are sent from a control unit to a disk unit which stores a parity record as information necessary for updating parity. The disk unit reads an old parity record and generates a new value of parity record based on the read old parity and the information received from the control unit. The generated new value is stored in an empty record on the storage medium to which a read/write head is first positioned after the generation of the new value and in which effective data has not been stored. In a disk array system, a time required to update the parity record due to the updating of the data record is reduced and a performance of the storage unit subsystem is improved.

Abstract: A method and apparatus for testing circuitry, such as a memory or a logic circuit, having a plurality of outputs, includes a built-in self-testing (BIST) test state machine for generating a plurality of address outputs, a plurality of multiplexers controlled by the address outputs of the test state machine, and a testing device for testing the plurality of outputs of the circuitry based on the address outputs of the test state machine. The plurality of outputs of the circuitry are input to the plurality of multiplexers and a number of outputs tested simultaneously is less than a total number of outputs of the circuitry.

Abstract: A memory device which tests the memory array under typical operating conditions. In one embodiment, the memory device incorporates a heating element to heat the memory array to a predetermined operating temperature, and a BIST (built-in self test) unit to test the memory array at the predetermined operating temperature. This may advantageously provide a method for detecting and repairing faulty memory locations that would not normally test faulty under initial power-up conditions. Broadly speaking, the present invention contemplates a memory device which comprises a memory array and a heating element on a substrate. The memory array is configured to receive a read/write signal on a read/write line, configured to receive an address on an address bus, configured to provide data to a data bus when the read/write signal indicates a read operation, and configured to store data from the data bus when the read/write signal indicates a write operation.

Abstract: A memory includes a built-in testing circuit for determining pass/fail of a memory portion and an identifier register for storing identification value for identifying the memory. The memory performs a testing operation according to a command provided from a controller via a send link and sends the result of that testing to a sync link. Thus, the memory controller can identify a defective memory cell. In this way, erroneous operation of the system due to a defective memory cell in a memory system can be prevented.

Abstract: A production operator interface is created using self-contained ActiveX controls each of which provide an interface to a specific part of the overall test system. These controls all communicate among themselves automatically. The production interface uses an ActiveX "tester control" which provides an application programming interface to the rest of the software control system. A library of self-contained ActiveX controls is provided which contains "operator controls" which may be "dragged and dropped" into an operator window to provide the operator with information and the ability to control the test system. In addition a semiconductor test system needs to be adapted to work with one or more different packaged device handlers or wafer probers which position a semiconductor device for testing by the tester. An ActiveX operator control allows an operator to select a handler driver from a library of handler drivers.

Abstract: A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.

Abstract: A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

Abstract: In a large system such as a parallel computer system, a scan device forms a scan path by hierarchically connecting input and output signal lines of integrated circuits, thereby enabling creating of a short scan path which contain only the necessary integrated circuits. This allows a scan test such as JTAG-SCAN to be effectively made.

Abstract: A semiconductor test system is capable of performing a simultaneous test for testing a plurality of memory devices at the same time as well as carrying out re-write operations in a page by page manner of the memory address, to reduce an overall test time. The semiconductor test system includes a hold means 5 which detects fail information in the output signal from a pass/fail judgement circuit 1, within a page of the memory address, and holds the fail information. A judgement means 11 is provided to determine, at the end of each page, whether the failure has occurred in each of the memory devices under test. A re-write control circuit 100 is provided for transmitting an output signal of the flip-flop 11 as a re-write prohibition signal 102. A plurality of re-write control circuits 200, 300 may be additionally provided corresponding to the number of devices to be tested.

Abstract: A dual channel readback recovery circuit includes a high resolution channel and a low resolution channel and a data latch. A logical filter in one or both channels rejects signals that are followed by other signals if they are spaced apart less than the rejection time interval allowed by the code used. Polarity qualifying logic rejects signals in the channel that are not matched in polarity.

Abstract: Fault tolerance in a redundant array of disk drives is degraded when error conditions exist in the array. Several methods for rebuilding data of the array to remove the degradation are described. Data rebuilding for entire disk drives and partial data rebuilds of disk drives are described. All rebuild methods tend to reduce the negative affect of using array resources for the data rebuild. In one method rebuilding occurs during idle time of the array. In a second method rebuilding is interleaved between current data area accessing operations of the array at a rate which is inversely proportional to activity level of the array. In a third method, the data are rebuilt when a data area being accessed is a data area needing rebuilding.