Abstract: A method and apparatus for performing block encoding in an asymmetrical digital subscriber line (ADSL) system uses a pipelined structure. The parity check circuit (116) contains a plurality of pipeline stages (201, 203, 205, and 207). Each stage contains an ADSL input data register (200, 202, 204, and 206) at a beginning of each stage and a carry register (208, 210, and 212) separating each stage. Each stage contains a plurality of carry circuits (214-220) which are serially coupled together by carry signals. The plurality of carry circuits (214-220) use generator polynomial root (.alpha.) processing involving serial carry propagation whereby the pipelining is implemented in the stages (201, 203, 205, and 207) in order to break the serial carry path from one long string to smaller segmented strings which are pipelined together. This pipelining is performed so that parity generation can occur at the higher frequencies required by ADSL systems.

Abstract: A decode register which receives a first plurality of input lines. If the decode register is not in a scan mode during a given clock cycle, the decode register is configured to convey a decoded output value in response to an input value conveyed on the first plurality of input lines. The decode register also includes a scan decode unit, which receives a second plurality of input lines. When operating in scan mode during a given clock cycle, the decode register is configured to convey a second decoded output value in response to a second input value conveyed on the second plurality of input lines. The second plurality of input lines comprise a scan input line and one or more feedback lines which each correspond to a value on the scan input line during a previous clock cycle. The decode register also includes an encoder which is configured to receive a value indicative of the second decoded output value.

Abstract: Soft errors generated at an active time are reduced by adding a small-scale circuit to a high performance LSI, such as a processor without reducing the performance of the circuit. The processor has individual logic circuits each having a plurality of stages of logic gates for outputting true signals and complement signals for the individual logic gates. A latch circuit latches the true and complement signals of the logic circuits separately and a compare circuit detects for an error by comparing the true and complement output signals of the logic circuits to determine if they are at the same logical signal level or not, just upstream of the latch in which the individual true and complement output signals of the final logic circuit stages are individually latched. When the compare circuit detects an error because the true and complement output signals are at the same logical signal level, a recovery process is executed.

Abstract: A digital write-and-read method and a signal processing apparatus wherein a write encoder includes a bit distribution circuit for dividing an input data block into n (n: 2 or more) series of bit strings and outputting them in parallel, a first coding circuit for executing predetermined coding for each of data series so distributed and a second coding circuit for converting the output bit series D1 to D3 of the first coding circuit to an n-bit channel code by looking up the previous channel code information, and wherein the second coding circuit executes coding by using a combination having a large Euclidean distance in a partial response equalization output taking inter-symbol interference of at least three bits into consideration as a pair.

Abstract: The present invention pertains to a method for analyzing a semiconductor chip design for determining potential voltage drop and electromigration problems. Initially, the semiconductor chip design is divided into a plurality of blocks. A block level verification is then performed based on the assumption that full voltage is being supplied to each of the blocks. Next, the blocks are modeled by an equivalent RC network. This RC network is then reduced into a simpler representation. The voltage drops are determined based on the reduced, equivalent model. The blocks are then reanalyzed with the supply voltage input to the blocks reduced according to the calculated voltage drops. Thereby, a more realistic simulation can be achieved.

Abstract: A circuit for read-enabling a memory device with checking of the minimum functionality conditions of the memory cells and reading circuits, particularly for non-volatile memories, having a structure for reproducing the operating conditions within the memory matrix to determine the minimum duration of the step for pre-charging the bit lines involved in the reading operation, the structure being adapted to generate a pre-charge step interruption signal that depends on the reaching of the minimum functionality conditions; a mechanism for generating a power-on-reset signal for enabling reading when the minimum functionality conditions for reading correctness are reached, the power-on-reset signal generating mechanism being adapted to drive a control logic mechanism as well as a reading control and stimulation mechanism.

Abstract: A data compare technique for detecting memory errors on a computer's memory subsystem is disclosed. The technique simulates memory intensive software to determine if memory errors occur when the computer's memory subsystem is subjected to heavy memory usage. The technique copies an extensive test file, performs checksums of the original and copied test files and compares the checksum of the original file to the checksum of each copied file to identify checksum differences. The checksum differences indicate the occurrence of a memory error.

Abstract: A method and apparatus for generating test data is presented. A data generator produces data using element specifications contained in an input script. The data generator includes a specification analyzer and data synthesizer. The data generator produces the data that includes varied combinations of the element specification generated in a particular order. Both the combination and the particular order in the generated sequence may vary in accordance with a specified method of data generation. Three methods of data generation--carry-out method, grey code method, and all-change method--are described.

Abstract: A mask ROM having a redundancy function according to the present invention comprises a plurality of redundancy memory cells subjected to data write processing using a laser trimmer, a bit line connected to each of the plurality of redundancy memory cells, a sense amplifier connected to the redundancy bit line, a redundancy bit setting section for holding a setting result, and a switch section for selectively outputting an output from the sense amplifier as it is and an inverted output thereof in accordance with the setting result.

Abstract: A process and implementing computer system in which a power-on self-test (POST) routine initially clears 203 a mask register 111 which is effective to mask or block data from being written to addresses in a synchronous DRAM or SDRAM 107. After disabling interrupts and caches, the tested SDRAM memory 107 is cleared to all "0"s. Sequential data byte lanes are tested by writing bits in a predetermined pattern to inject errors at predetermined bytes in SDRAM, setting selected mask register bits and then writing all "0"s to the predetermined addresses. The tested memory locations are read and compared with the predetermined pattern for errors. Detected errors are noted by recordation and the memory locations are cleared as the method recycles until all of the data byte lanes have been tested and the results recorded.

Abstract: A method and apparatus for using a test signal being computed by applying a combinational test pattern generation tool to a model of the apparatus in which at least one of an at least one sequential device is modelled as a non-sequential device, the apparatus having a first scan cell configured to receive the test signal and drive a first signal in response to a first clock phase; a sequential logic block having the at least one sequential device, the sequential logic block being configured to generate a second signal, at least one of the at least one sequential device being a non-scan cell.

Abstract: A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.

Abstract: An object of the present invention is to provide a microcomputer capable of checking the data stored in a read only memory (ROM) integrally formed therein even without using any additional testing device, but an external ROM. In the test mode, a test signal TS to be fed to an external terminal 15 is set to a logic "1". By this operation, the output signal of a register 13 is fed to the address terminal A of the internal ROM 16 by way of a selector 14. Further, the data read out from the ROM 16 is outputted to a register 18 through a selector 17. On the other hand, by connecting the external ROM 30, in which a test program is stored, to an address terminal 21 and a data terminal 22. The CPU 11 can carry out the test program stored in the external ROM 30. By reading and comparing the data stored in the ROM 16 and the data stored in the external ROM 30 to be compared by the test program, the data in the ROM 16 can be checked.

Abstract: A method for coupling a linear impedance control (LIC) type output driver to IEEE 1149.1 boundary scan circuitry includes entering a boundary scan load mode to load a test pattern into a chain of boundary scan registers (BSRs). The test pattern includes values corresponding to output enable and data signals according to the IEEE 1149.1 standard. Then these data and output enable signals from the BSRs are converted into test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the LIC driver. These test "q.sub.-- up" and "q.sub.-- dn" signals are selectively provided to the LIC driver during boundary scan testing of the LIC driver. In a further refinement, the method enters a boundary scan capture mode to capture the response (i.e., the functional q.sub.-- up and q.sub.-- dn signals) of the circuit under test to input test patterns shifted into the BSRs. The functional q.sub.-- up and q.sub.-- dn signals are converted into response data and oe signals complying with the IEEE 1149.

Abstract: A computationally simple yet powerful forward error correction code scheme for transmission of real-time media signals, such as digitized voice, video or audio, in a packet switched network, such as the Internet. The invention appends to each of a series of payload packets a single forward error correction code that is defined by taking the XOR sum of a preceding specified number of payload packets. The invention thereby enables correction from the loss of multiple packets in a row, without significantly increasing the data rate or otherwise delaying transmission.

Abstract: A semiconductor memory device comprising redundancy memory elements for functionally replacing defective memory elements, redundancy circuits for operating said functional substitution of the redundancy memory elements for the defective memory elements, and operation mode control circuits for controlling the memory device to operate according to a plurality of operation modes, said plurality of operation modes comprising a memory read mode and redundancy test modes for testing the redundancy circuits. The memory device comprises an internal shared bus of signal lines that when the memory device is operated in said read mode is used to transfer read data signals to output terminals of the memory device and when the memory device is operated in one of said redundancy test modes is used to transfer redundancy signals, depending on the redundancy test mode, to the output terminals of the memory device.

Abstract: In a memory device equipped with a redundancy circuit comprising at least one redundancy memory register storing a defective address of a defective memory element and an identifying code suitable for identifying a portion of a matrix of memory elements wherein the defective memory element is located, a circuit for transferring redundancy data of a redundancy circuit inside the memory device is provided. The circuit comprises a shared bus of signal lines provided in the memory device to interconnect a plurality of circuit blocks of the memory device and for transferring signals between the circuit blocks. The shared bus can be selectively to the various circuit blocks, and a bus assignment circuit associated to the redundancy circuit is provided for assigning, during a prescribed time interval of a read cycle of the memory device, the shared bus to the redundancy circuit whereby in the prescribed time interval the identifying code stored in the redundancy memory register can be transferred onto the shared bus.

Abstract: In a semiconductor device formed on a semiconductor wafer, writing unit writes a result signal into an unvolatile memory. A testing unit tests whether or not an execution unit of the semiconductor device executes a predetermined function correctly and produces the result signal. The result signal is used to diagnose the semiconductor devise itself. The execution unit may be included in the unvolatile memory.

Abstract: A computer system includes a memory requester that interfaces with a memory module that includes memory portions. An error map that identifies the defective memory portions of the memory module is created and stored in the computer system. Using the error map, a remapping table that maps each of the defective memory portions to a non-defective memory portion in the memory module is created and then stored. In response to receiving from the memory requester a request for access to a requested memory portion of the memory module, a determination is made from the error map whether the requested memory portion is one of the defective memory portions. If the error map indicates that the requested memory portion is one of the defective memory portions, then a determination is made from the remapping table the non-defective memory portion to which the requested memory portion is mapped.

Abstract: Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of the integrated circuit in which the boundary scan cells are provided. The latchable input and output buffers provide the input and output boundary scan cells with a low overhead latching function.