Abstract: When protected network connections on a connection oriented network are disrupted because a network resource fails (e.g. the severing of a fiber cable upon which multiple links are multiplexed), they must be rerouted around the network failure. This invention expedites this rerouting and permits it to be carried out in a distributed manner similar to conventional routing. Advantageously, the amount of link bandwidth reserved for rerouting of failed connections is reduced relative to conventional methods.For each protected connection, for each anticipated failure condition, a "contingent path" is selected shortly after the connection is established. This contingent path is then used to reroute that connection in the event of the occurrence of that failure condition.

Abstract: A method of and system for creating telecommunication system test cases. The system includes a first user interface for the input of test case information for the creation of at least partially complete test case outlines. The test case outlines are stored in a test case outline storage. A lab data database contains laboratory data. The system includes a process for searching the database of laboratory data and creating completed test case outlines from partially completed test case outlines. A rules database contains rules for generating test case output data from test case outlines. The system includes a process for applying rules from the rules database to test case outlines to generate test case output data.

Abstract: A failure analysis memory for storing failure information representative of a test result of a semiconductor memory under test is divided into a plurality of blocks with compacted addresses, and a compaction memory having areas corresponding respectively to the blocks of the failure analysis memory is prepared. Data indicative of a failure cell in any one of the blocks of the failure analysis memory is written in an area of the compaction memory which corresponds to the any one of the blocks. Minimum and maximum addresses of addresses at which failure cells are present in the blocks are determined, and failure data is read from the failure analysis memory in a range between the minimum and maximum addresses of each of the blocks, which correspond to the areas of the compaction memory which store the data indicative of a failure cell.

Abstract: A multirate generator for generating a rate signal and a multirate signal having a subrate period and a subrate number which are set for each period of the rate signal, which comprises a rate signal generation unit, a multirate signal generation unit, and a multirate number detection unit. The multirate generator operates the rate signal generation unit and the multirate generation unit by means of the same clock and makes the rate signal generation unit and the multirate generation unit generate, respectively, a rate signal and a multirate signal, to generate a rate signal and a multirate signal which have been timing-adjusted without delay elements and the like, and without requiring a timing adjustment. The rate data, multirate data and multirate number data may be optionally set, to enable outputting a desired rate signal and a desired multirate signal.

Abstract: An operation recorder that stores the operating conditions of an integrated circuit chip. The recorder includes an on-chip oscillator and an external reference clock. The frequencies of these two sources are compared and a value indicating chip operating conditions is output to a memory. The memory contains a number of values which store the operating history of the chip.

Abstract: A test pattern generator for testing a semiconductor memory with a multi-bit data width and high speed is realized with low cost and small size. The pattern generator includes a data operator having a 1/n width of the data width of a device to be tested, a register which is formed of n bits whose data is established by an instruction memory, and n control logic circuits for controlling the passage of data signals based on the output signal of the register. The control logic circuits include AND gates which transmit the output signal from the data operator based on the output signal of the register and OR gates which provide fixed output signals. The pattern generator further includes an exclusive OR gate for inverting the data based on an output of a flag register.

Abstract: A pattern generator that makes it possible to use various option pattern generators (PGs) without changing hardware is realized. To accomplish this, an option circuit includes an option PG initial clock control section that generates an initial clock signal in synchronism with a clock signal to initialize the option PGs; a plurality of option PGs selectively receive one of a plurality of clock output signals of a clock output control section and generate pattern and clock signals; and in a multiplexer which selects one of output signals from the plurality of PGs through an instruction from a select register 24, and a FIFO section which receives a signal from the multiplexer as write data and a write clock, and an output signal of a read clock control section as a read clock, and outputs a signal to a logic circuit as the option PG output signal.

Abstract: A method for detecting and compensating for missing and/or incorrectly inserted cells on the reception side in the transmission of ATM cells with an adaptation layer AAL of type 1, the cells being assigned a sequence number and an error detection and correction code which indicates whether or not the sequence number, and additional information dependent thereon, have been transmitted correctly. It is decided on the basis of these data whether a cell is rejected or transmitted on, and whether there are missing or incorrectly inserted cells. A decision regarding the acceptance or the rejection of a received cell is taken directly without waiting for a following cell, while the possible decision as to whether a cell is preceded by one or more missing cells or whether a cell is an incorrectly inserted cell, is taken after the reception of a following cell.

Abstract: A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

Abstract: A method of testing an integrated circuit chip comprised of applying to and storing a first test pattern of data on the chip, applying a second test pattern of data to the chip which corresponds to the first test pattern, comparing the stored test pattern with the second test pattern on the chip, and indicating a test fault on a test pad in the event at least one bit of the first and second test pattern differ from each other.

Abstract: Disclosed is a loadboard that includes a plurality of channel pins that are arranged on the loadboard. The plurality of channel pins are electrically routed on the loadboard to a receptacle that is configured to receive I/O pins of an integrated circuit chip. The loadboard further includes a programming and test circuit that is integrated on the loadboard, and is coupled to a set of the plurality of channel pins to enable communication with the integrated circuit chip. The programming and test circuit includes a programming sub-circuit for communicating a plurality of voltage levels set by a programming vector to the integrated circuit chip, and a bias sub-circuit for communicating a plurality of bias voltage levels set by the programming vector to the integrated circuit chip.

Abstract: An integrated circuit (IC) tester employs both central and distributed data sources for controlling tester operation during a test. The tester includes a master controller, a central scan data source, and a set of tester nodes. Each tester node carries out a sequence of test actions at an IC terminal, each action being defined by a data word (test vector). Before the test sets of vectors are written into vector memories in the nodes and separate control data is loaded into registers in each node. During the test, the scan data source sends scan data words concurrently to all tester nodes, and each node stores them. The master controller sends a similar instruction to each tester node during each cycle of the test. Some instructions reference a vector stored in the node and instruct all tester nodes to carry out the action indicated by the referenced vector.

Abstract: A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality of modes which identifies processor state information to output onto the plurality of external pins; and a bus interface unit for communicating data to the external pins of the processor and for detecting an idle bus cycle. The bus interface unit outputs processor state information according to the identified mode onto the plurality of external pins in response to detecting an idle bus cycle.

Abstract: A method and apparatus for serially programming or testing a programmable logic device. In one embodiment, the method comprises the steps of: instructing the programmable logic device, in one instruction, to load program data, load address information and program the program data into a memory location defined by the address information; loading the program data into a data storage element and the address information into an address storage element; and programming the program data into the memory location. The novel method further comprises the step of instructing the programmable logic device, in one instruction, to read verify data from the memory location, to compare the verify data with the program data and to program the program data into the memory location. The novel method further comprises the steps of comparing the verify data with the program data and generating a verify signal.

Abstract: A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.

Abstract: A method of cache testing and fault correction is implemented subsequent to wafer dicing. Cache testing is moved from wafer level to the built-in self test (BIST) at machine level. The BIST is utilized along with cache redundancy for fault correction. The processor initiates a cache line test using BIST upon power-up. When the processor is powered up and the test mode pins are set for the array test, the array BIST test begins. The BIST traverses the array and tests each word line for hardware faults. Upon detection of a fault, the current address is stored in one of N fault address registers contained in the processor. These fault address registers are used to address redundant cache lines and therefore act as "soft" fuses. The entire cache structure is traversed in this manner with the addresses of any line faults being stored. If the number of found faults, indicated by stored addresses, are less than the number of redundant fault lines, then the processor self test will proceed to the next test.

Abstract: A method is provided for operating a scan chain in a semiconductor device having a plurality of serially connected logic blocks, an output from a first logic block being coupled to an input of a first latch, the output from the first latch being coupled to the input of a second logic block, an output of the second logic block being coupled to an input of a second latch, the method comprising: detecting a test enable signal; if the test enable signal is active: detecting the output of the first latch, and setting the output of the second latch to the same state as the detected output of the first latch, independently of the state of the output of the second logic block; if the test enable signal is inactive: setting the output of the second latch responsive to the output of the second logic block.

Abstract: There is provided a memory testing apparatus which can read out the information of failure memory cells of a tested memory from a failure analysis memory having the same memory capacity as that of a memory under test and can complete in a short time period the process for computing the classified total of the number of memory cell failures occurred. The memory area of the failure analysis memory is subdivided into a plurality of memory blocks, a flag memory having the same number of addresses as the number of the subdivided memory blocks is provided, and an address is assigned to each of the memory blocks. When a failure occurs in one of the memory blocks, a logical "1" indicating failure information is written at an address of the flag memory corresponding to that memory block.

Abstract: A production operator interface is created using self-contained ActiveX controls each of which provide an interface to a specific part of the overall test system. These controls all communicate among themselves automatically. The production interface uses an ActiveX "tester control" which provides an application programming interface to the rest of the software control system. A library of self-contained ActiveX controls is provided which contains "operator controls" which may be "dragged and dropped" into an operator window to provide the operator with information and the ability to control the test system. In addition a semiconductor test system needs to be adapted to work with one or more different packaged device handlers or wafer probers which position a semiconductor device for testing by the tester. An ActiveX operator control allows an operator to select a handler driver from a library of handler drivers.

Abstract: A semiconductor integrated circuit device comprises, on a semiconductor chip, a large-scale memory as a main memory, a controller for controlling at least inputting data from the outside of the chip to the large-scale memory, and outputting data from the large-scale memory to the outside of the chip, and a self-test circuit for testing the large-scale memory. The self-test circuit includes a rewritable EEPROM, into which a self-test sequence is written. The self-test circuit tests the large-scale memory in accordance with the self-test sequence written in the EEPROM.