Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs a remod/demod sequence detector guided by an error syndrome of an error detection code (EDC). The remod/demod sequence detector comprises: a conventional trellis type maximum likelihood sequence detector, such as a Viterbi detector, for detecting a preliminary binary sequence from the channel sample values; a syndrome generator for generating an error syndrome in response to the preliminary binary sequence; a remodulator for remodulating the detected binary sequence into a sequence of estimated ideal sample values; a sample error generator for subtracting the channel samples from the estimated samples to generate a sample error sequence; an error pattern detector for detecting potential error events in the sample error sequence; and an error corrector for correcting the preliminary binary sequence when the error syndrome indicates that an error occurred.

Abstract: A built-in self-test (BIST) method and apparatus for digital integrated circuits (ICs) and for systems including multiple ICs, measures signal propagation delays in combinational and sequential logic, set-up and hold times, and tri-state enable/disable times, from any circuit node to any other circuit node including pin-to-pin and from one IC to another. The IC under test is provided with two test bus conductors passing near every circuit node of interest and connected thereto by switches or buffers. During test, an oscillator is created including the test bus, a constant delay, counters, and a delay path of interest or a reference path. The delay path of interest may include e.g. an analog filter. The oscillation period of the oscillator when the reference path is selected is subtracted from the oscillation period when the oscillator includes a delay path of interest. A circuit automatically accommodates inverting and non-inverting paths.

Abstract: An address detection circuit includes for each bit to be detected, a plurality of antifuse legs connected in parallel. Each of the antifuse legs includes a separate isolation transistor, so that each of the antifuse legs can be separately disabled. For blowing, only one of the antifuse legs is enabled at a time. During conventional operation, all of the antifuse legs are enabled so that the overall resistance of the antifuse legs equals the parallel combination of the resistances of the blown antifuses. Because the parallel combination of the blown antifuses is always less than or equal to the lower of the resistances of the antifuses, only one of the antifuses need be blown properly for the parallel combination to operate properly.

Abstract: A pattern data generating system solves a problem of a conventional pattern data generating system in which the total processing time is prolonged. The present pattern data generating system includes a parallel processing number calculator for computing the number of parallel processes to be used by a region divider that sequentially distributes the split pattern data. A group of pattern data generators generate pattern data in parallel processes. A pattern data combiner combines the pattern data output from the pattern data generators. A parallel processing controller controls the processing.

Abstract: An LSSD MUX D flip flop includes a multiplexer, a master latch L1 and a slave latch L2. The inputs to the multiplexer are functional data D, scan data I, and the control is scan enable SE. The L1 master latch receives its input from the output of the multiplexer and is clocked by the NAND of a -FLUSH (-A CLOCK) with an +EdgeClock (-C CLOCK.) The L2 slave latch receives its data input from the output of the L1 master latch and is clocked with the AND of -FREEZE (B CLOCK) and +EdgeClock. The output of the flip flop is the output of the L2 slave latch. This flip flop structure supports edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.

Abstract: The method for initiating and controlling integrated circuit testing includes providing a plurality of test modes with each test mode having a corresponding test mode address vector. A test enable cycle is enabled by executing an unlock enable cycle with a predetermined lockout address vector and at least one particular test mode of the plurality of test modes is initiated by executing the test enable cycle with a test mode address vector corresponding to the at least one particular test mode. The method may also include latching the at least one particular test mode of the plurality of test modes, detecting supply voltage applied to the integrated circuit, and clearing the latched at least one particular test mode as a function of the detected supply voltage. The test enable cycle may also include a supervoltage test enable cycle executable with a supervoltage.

Abstract: A test device for testing a plurality of Digital Signal Processor Integrated Circuits Incorporated as a finished product in a digital video apparatus comprises: a plurality of Digital Signal Processor Integrated Circuits (DSP ICs) for processing a signal from a test signal generator as a digital signal and outputting the digitally processed signal, the test signal generator being disposed at an input end of the plurality of DSP ICs; a monitor for monitoring an output from the DSP IC being tested. It is possible to check in a simple manner the operating state of each IC connected to other DSP ICs as well as the production and assembly state of the PCB as a finished digital video apparatus. Furthermore, it is possible to check for damage of the parts or an error which may be generated during connection of the ICs to the lines on the PCB in the manufacturing of the products as well as defects caused during shipping of assembled IC components in a DSP apparatus.

Abstract: An improved method of simulating the testing of integrated circuits is provided. A database of desired connections between a tester unit and a DUT for different downbonds is accessed by a multiplexer which sets up the desired connections. The system automatically makes the correct connection for each downbond without manual intervention from the user as was required in traditional simulator systems.

Abstract: A multilevel non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state or in the case of a flash memory, reading a sector of the memory, saving data from the sector in a buffer, erasing the sector, and rewriting the data from the buffer back in the sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months.

Abstract: According to the present invention, methods for testing interconnections on an electronic assembly in accordance with the disclosed embodiments eliminate some or all signal line contention during boundary scan testing. Each of these methods assumes that a first sequence of test patterns for testing the interconnects has been generated. A method in accordance with the first embodiment determines a safe pattern, and inserts the safe pattern between every two patterns in the first sequence of test patterns to generate a second sequence of test patterns. A method in accordance with the second embodiment analyzes the first sequence of test patterns, determines when a transition between two test patterns may cause possible signal contention, and inserts a safe test pattern between the two to generate a second sequence of test patterns. When a transition between two test patterns may potentially cause contention, the transition is said to be unsafe.

Abstract: A method of testing a semiconductor memory device using a parallel march pattern method of testing. All of the memory bits in a memory device are programmed to a first logic state. All of the memory bits in selected rows are programmed to a second logic state. All of the memory bits in rows adjacent to the rows programmed to the second logic state are read to determine if the memory bits programmed to the second logic state have caused the memory bits programmed to the first logic state in the adjacent rows to change logic state. The selected rows are determined by a periodicity value that can be values such as 4, 8, or 16. The periodicity determines the number of clock cycles needed to test the entire memory device. A periodicity of 8 requires only 8 clock cycles to test the entire memory device, regardless of the size of the memory device. The parallel march pattern method of testing can be by rows, by columns or by diagonals.

Abstract: The present invention pertains to an apparatus and method for determining at most four error locations of RS encoded data read from a storage medium. The error location polynomial solver includes a controller, a multiplexer, storage registers, a data flow control unit, and various GF(256) arithmetic units. The GF(256) arithmetic units include GF(256) multiply unit, a GF(256) logarithmic ROM, a GF(256) anti-logarithmic ROM, a GF(256) square root unit, a GF(256) quadratic root finder, and a specialized integer division unit. The controller directs the operation of each of these components to perform one or more equation solver procedures that determine the appropriate number of roots. In an embodiment of the present invention, the controller is implemented as a state machine. The controller receives four coefficients representing an error location polynomial. The degree of the error location polynomial is determined in order for the controller to execute an appropriate equation solver procedure.

Abstract: A memory test system is to perform two or more comparison operations within one test cycle. The memory test system includes a pattern generator for generating test data patterns to be supplied to the memory device under test, a data selector for providing the test data patterns in a parallel fashion at a plurality of ports, a test data multiplexer for selecting one of the test data patterns at the plurality of ports to supply a plurality of test data patterns to the memory device in a series fashion within each of the predetermined test cycle, an expected value select circuit for selectively providing the test data pattern as expected value data in a parallel fashion, and a logic comparator for receiving, in a parallel fashion, an output signal from the memory device under test generated as a result of the test data patterns and comparing, in parallel, the output signals with the expected value data from the expected value select circuit.

Abstract: A three-value data storing semiconductor memory system, which has a plurality of memory cells capable of storing a three-value data item, comprises a first interface for receiving a plurality of binary data items of a first type, each including 2.sup.m binary data items (m=1, 2, 3, . . . ), from an external device, a control circuit for processing the binary data items of the first type input to the first interface, in units of 3k data items (k=1, 2, 3, ), converting each data unit consisting of 3k data items, to 4k binary data items of a third type, and outputting the binary data items of the third type in units of 2.sup.n binary data items (n=0, 1, 2, 3, . . . ) as binary data items of a second type via a second interface.

Abstract: The present invention discloses a method and apparatus for providing error detection capability for initialization data stored in a non-volatile memory used in a video monitor. The method comprises the steps of: (1) storing N test values in N distinct locations in the non-volatile memory; (2) reading the N stored test values from the non-volatile memory, each test value being read for K times; (3) selecting N read test values representative of the N stored test values; (4) comparing the N read test values with N corresponding check values; and (5) if the N read test values are equal to the N corresponding check values, reading the initialization data from the non-volatile memory.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A flash memory test system supplies test data to a flash memory under test to write the test data in the specified address of the memory and compares the data in the specified address with expected data to determined whether the data writing for the address is completed. If the data writing is unsuccessful, the write operation is repeated until the test data is correctly stored in the address or the predetermined maximum number of the write operation is reached. The number of repeated write operation is recorded for each address and displayed relative to the physical image of the flash memory under test.

Abstract: An integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In the test mode of preferred embodiments in which the circuit is an integrated memory chip, the test mode switch is closed so as to connect an input/output (I/O) pad directly with a selected memory cell (so a current/voltage characterization of the cell can be obtained). In the normal operating mode of these embodiments, the test mode switch is open and it isolates the I/O pad from direct connection with the selected cell even under the condition that a transistor of the test mode switch undesirably becomes conductive (e.g., due to low voltage on the I/O pad, inductive coupling, or the like).

Abstract: In a memory testing device of a construction wherein various pieces of pattern data output from a pattern generator are taken out in a desired order and converted into a test pattern signal having a real waveform for application to each pin of a memory under test, the pattern selector provided for each I/O pin of the memory under test comprises plural registers having stored therein pattern selection control signals that designate patterns to be selected, a first multiplexer for selecting that one of the registers designated by a register selection control signal PJ generated by the pattern generator, and a second multiplexer that is controlled by the pattern selection control signal selected by the first multiplexer to select a pattern from the pattern data output from the pattern generator.

Abstract: A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.