Abstract: An improved circuit tester allows for increased storage of test vectors in existing memory structures by noting where segments of test vectors repeat and storing such segments only once, then further utilizing memory space corresponding to otherwise unused test channels. Switching circuitry is included to selectively forward signals to and from a designated, multi-source conductor.

Abstract: A method of testing a digital memory comprised of bit storage locations, comprising writing a bit to a first bit storage location, then driving the stored bit sequentially through a plurality of the bit storage locations, reading a last bit storage location of the plurality of bit storage locations, and testing a bit read from the last bit storage location.

Abstract: A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.

Abstract: A test coverage tool determines the adequacy of a set of test vectors for a state simulator for exercising logic paths in a logic circuit design. The speed coverage tool generally compares state data from a state simulator and timing data from a timing simulator in order to validate whether a test vector covers a simulated timing path. In architecture, the speed coverage tool includes first logic configured to acquire state data from the logic circuit design that has been produced by a state simulator based upon test vectors. Second logic associated with the tool obtains timing data concerning one or more logic paths of the logic circuit design that has been produced using a timing simulator. Third logic associated with the test coverage tool is configured to determine a transition score by comparing the timing data with the state data. The score is indicative of the adequacy of a set of test vectors.

Abstract: The invention comprises a method and system for testing memory in an interface system 10 coupling a parallel host bus 30 to a serial bus 20. The system comprises a random access memory 70 having a plurality of memory locations for temporarily storing data received from either the parallel host bus 30 or the IEEE 1394 serial bus 20, the random access memory 70 being logically divided into a transmit memory portion and a receive memory portion. The interface also comprises a transmission control unit 40 operable to control transmission of data from the parallel host bus 30 to the IEEE 1394 serial bus 20. The transmission control unit 40 is further operable to access the transmit memory portion of the random access memory 70. The interface also comprises a reception control unit 50 operable to control reception of data by the parallel bus 30 from the serial bus 20. The receive control unit 50 is further operable to access the receive memory portion of the random access memory 70.

Abstract: A magnetic disk certifier according to the present invention is featured by comprising a write circuit for writing a test data having a period which is 1/n of a bit period of the test data, error of which is to be detected, in a magnetic disk, where n is an integer equal to or larger than 2, a read-out circuit for reading out the test data written in the magnetic disk, a comparator circuit for producing a detection signal by comparing a read-out signal read out from the read-out circuit with a predetermined signal or a predetermined reference level and an error detector circuit for detecting an error by receiving the detection signal from the comparator circuit with a period which is n times the bit period of the test data written in the magnetic disk, a bit data of an error detected by the error detector circuit being used as an error signal by converting each bit of the bit data into n bits.

Abstract: A method and arrangement for testing circuit boards (60) by creating one or several reference patterns to be compared with a test pattern. The arrangement is provided with at least one measuring probe (50), which cooperates with the circuit board (60), for measuring at least one reference signal or test signal on a reference circuit board and a test circuit board (60) respectively. Further, the arrangement is provided with an analyzer (10,30), which cooperates with the measuring probe (50), to pass on the reference signal or the test signal, whereby the analyzer (10,30) first analyzes the reference signal or the test signal at one frequency and then transforms the reference signal or the test signal to a reference pattern and test pattern respectively. Furthermore, the arrangement is provided with at least one memory (20) which cooperates with said analyzer (10,30) to register said reference pattern or test pattern.

Abstract: A modular and highly available RAID system has a fiber channel arbitrated loop (FC-AL) interface coupled with a disk array. Fault-tolerant operation is assured. The system provides dual and isolated arbitrated host and storage device loop circuits for redundant, independent input/output (I/O) paths to local and/or remote host computers. Each loop includes bypass circuits which prevent the failure of any device (host computer or storage device) from affecting the operation of loop. Orthogonal data striping may be used to further assure data integrity.

Abstract: The present invention provides method of encoding an electronic memory; multiple digital values are prioritized; respective digital values are associated with respective memory locations of the electronic memory such that there are multiple memory locations each associated with two or more different digital values; and respective digital values are loaded into respective memory locations of the electronic memory in order from lowest priority digital value to highest priority digital value wherein each respective digital value is loaded into all respective memory locations that are associated with such respective digital value.

Abstract: A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns, and a pair of complimentary digit lines being provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complimentary data lines. The data lines are coupled to respective inputs of a sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data is selectively coupled to the inputs of the sense amplifier from the complimentary digit lines for an addressed column. In a test mode, the multiplexer connects an I/O line for one array to one of the data lines and an I/O line for the other array to the other data line.

Abstract: A memory circuit having a plurality of regions. A first rearranging circuit, controlled by a control circuit, rearranges plural bits of data having different significances when a first of the regions includes a defective portion and a first one of the plural bits is to be written into the first region, so that a second of the plural bits having lower significance than that of the first bit is written into another one of the plurality of regions. A second rearranging circuit, controlled by the control circuit, rearranges the plural bits of data read out from the memory circuit so that the first and second bits are returned to correct positions.

Abstract: A process and implementing system is provided for conducting a memory test for isolating and identifying failed cache memory modules in a memory subsystem of a computer system. The methodology initially selects 303 a block of memory which is twice the size of the cache 105 being tested. The cache 105 is then disabled 305 and a first test is performed 307 on the selected block of to isolate byte addresses of individual bit failures. If bit failures are detected 308, the appropriate byte address is mapped 310 and the test is ended 321. If no bit errors are detected in the first test, the cache is enabled 309 and a second test is performed and the block is tested 311 for failures. Any detected failures are assumed to be cache failures and the appropriate byte address is mapped 315. The cache is again disabled 317. An appropriate message is then displayed 319 to indicate the results of the testing.

Abstract: A computer system comprises a host processor, host memory, and a mass storage device interconnected via a high-speed data bus. An operating system and a driver for the mass storage device are implemented on the host processor. The mass storage device is capable of being connected to the computer system via the data bus, such that a portion of the host memory is allocated for use by the mass storage device; the mass storage device uses the host memory portion for one or more particular mass storage device operations; and the operating system and the driver are unaware of how the mass storage device uses the host memory portion. In a preferred embodiment, the mass storage device requests and the host processor allocates a portion of host memory for exclusive use by the mass storage device to perform such functions as predictive failure analysis, maintenance of deallocated sector lists, and data prefetching.

Abstract: A method and apparatus for automatically generating test patterns for a circuit design using a number of data processing elements. The present invention reduces the wall time required to generate the test patterns for the overall circuit design by partitioning the design into a number of partitions, distributing the partitions to a number of data processing elements, and generating test patterns for each partition on the corresponding data processing elements. The present invention automatically assembles the resulting local test patterns to reflect the scan structure of the overall circuit design.

Abstract: A fault tolerant computer system includes a number of lockstep subsystems, each of which comprises a parallel input signature generator, used for data compression to allow practical comparison of the operation of internal modules of the lockstep subsystem, and a logic analyzer which stores the outputs of the internal modules of the lockstep subsystem. A signature comparator is connected to receive the signatures from the signature generators of the individual lockstep subsystems. The signature comparator generates a trigger signal for triggering the logic analyzers on detecting a difference in the signatures. The logic analyzers store enough states to include the first difference from a module following a detected difference in the signature outputs. The logic analyzer traces are searched automatically after an out-of-sync event to locate the first difference in operation and to determine which internal module provided the faulty output and then that module is labelled as broken.

Abstract: A method for programming an in-system programmable logic device (IsPLD), using an automatic tester, includes the steps of: (i) expressing a fuse map for an IsPLD in the form of one or more test vectors to be applied in an automatic tester; (ii) including in a system board unprogrammed the IsPLD; (ii) mounting the system board on an automatic tester in a configuration for system testing; (iii) receiving into the automatic tester the test vectors; and (iv) and apply the test vectors to program the IsPLD. The system board with the IsPLD so programmed can proceed immediately to final test. In addition, a method is provided to translate a JEDEC file to a bit stream file, thereby achieving a eight-fold saving in storage requirement.

Abstract: The present invention is to provide a delay correction circuit for a semiconductor tester which can decrease a circuit size and electric power consumption in a timing correction part. To achieve this goal, a variable delay element which corrects the phase difference stemming from the common parts of test stations is provided at an output of a waveform controller. At an output of a waveform output controller which generates the signal determining whether a signal should be applied to the test stations, flip-flops are provided which perform an inter-leave function. A gate circuit is provided which combines each unit of the inter-leave function based on the output signal of the variable delay element. An AND gate is provided which takes the logical AND between the output of the gate circuit corresponding to the test station and the output of the variable delay element. A variable delay element which corrects the phase difference stemming from each test station is provided at the output of the AND gate.

Abstract: A circuit including analog circuitry, digital circuitry partitioned from the analog circuitry, and a boundary scan cell chain along the boundary between the analog and digital circuitry. The chain can be controlled to decouple the analog circuitry from the digital circuitry and supply selected test signals to nodes along the boundary between the analog and digital circuitry during testing. Typically, the circuit is an integrated circuit having external pins for asserting signals directly to and receiving signals directly from each of the analog circuitry, digital circuitry, and boundary scan cell chain. Preferably, each cell of the chain comprises a first multiplexer, a flip-flop, and a second multiplexer having an input coupled to the flip-flop's output, another input coupled to one of the analog circuitry and the digital circuitry, and an output coupled to another of the analog circuitry and the digital circuitry.

Abstract: A memory unit for storing failure data of a semiconductor memory under test comprises a plurality of interleaved DRAMs. A buffer memory temporarily stores failure data to be stored into the DRAMs and addresses thereof. The DRAMs are associated respectively with storage controllers which store failure addresses whose row addresses correspond to the DRAMs, among inputted failure addresses, into buffer memories associated respectively with the DRAMs. Write controllers are associated respectively with the DRAMs, for reading the failure data from the buffer memories and writing the failure data into the DRAMs in a high-speed write mode.

Abstract: A failure diagnosis apparatus is provided which predicts failure locations in a CMOS integrated circuit in which an Iddq has been discovered, this apparatus having a test pattern storage unit 1 for storing test patterns used to perform a functional test of the CMOS integrated circuit, an LSI tester 3 which performs a functional test and an Iddq test on the CMOS integrated circuit based on the test patterns, a test results storage unit 6 to store test results, a circuit data storage unit 2 to store various information with regard to the device under test, a logic simulator 5 for receiving the above-noted test patterns and circuit data and performing a logic simulation of the internal operation of the circuit, a simulation results storage unit 7, and a failure location judgment unit 8 for outputting the diagnosis results based on test results and simulation results.