Abstract: A method and circuit are provided to detect if any bit stored in a given location in a memory is different from the data expected. The circuit includes logic to read each of the bits stored in the cells at given locations from memory and to generate a fail signal based on the data expected to be stored if the stored data is different from the expected data. The circuit also preferably includes logic to compare the True data and expect data read from each cell and generating the fail signal if they are the same. Additional logic circuitry is also preferably provided which determines if a node of the circuit remains in a precharged condition.

Abstract: A bit error measurement system provides means for generating test patterns, multiplexing means and means for specifying and recording a pattern position. In a first aspect, a bit error measurement system has a pattern generator having M channels of pattern generation and a pattern generation controller 10 for controlling the pattern generation in the M channels so that when one channel is selected to generate a pattern the other channels are controlled to be waiting. In a second aspect, a clock frequency difference detector 150 is provided for counting a frequency of an input clock 111 and comparing the results with the frequency at the time of previous switching to detect whether the frequency change is greater than a predetermined value to judge whether the system is in a measurement state and to permit or prohibit a switching operation of a clock switch circuit.

Abstract: There is provided an erasing device for erasing the recorded signal in each recording block on a recording medium such as a still video floppy which can individually record the signal into each of the recording blocks. The erasing device comprises: a discriminating circuit to discriminate a recording state of each recording block; an erasing circuit to generate an erasing signal; and a controller to control the erasing circuit in accordance with the result of the discrimination of the discrimination circuit. With this device, a state in which the memory area on the medium is erased can be obtained in a short time using little energy.

Abstract: A method and system for generating a test suite for a computer program. The computer program comprises program statements and program variables, including at least one input statement having one or more input variables, that are grouped into code blocks and stored in a program database. The test suite comprises sets of inputs. Each of the sets of inputs corresponds to each of the input statements. The program statements corresponding to a candidate code block are read from the program database. Each of the input variables for each input statement and each of the program variables are represented in symbolic form as a symbolic memory value and transforming each program statement dependent on such an input variable into a symbolic expression. A trial set of inputs for each of the input statements is created by finding a solution to the symbolic expression comprising actual input values corresponding to each symbolic memory value using dynamic symbolic exeuction.

Abstract: A semiconductor memory device includes: a plurality of sectioned memory arrays; a comparing circuit; and a predetermined terminal, and configured so that the test mode, the same test data is written in simultaneously into a plurality of memory arrays, and when the written data is read out, the data is read out simultaneously from a plurality of memory arrays so that the comparing circuit compares the simultaneously read-out data outputs, if the result of the comparison shows agreement, the data itself is outputted through the predetermined terminal, while if the result of the comparison shows disagreement, the predetermined terminal is set into a high-impedance state, or the predetermined terminal is made to output a particular voltage other than the voltages representing the `1` level and the `0` level.

Abstract: The invention provides a test system of a fault detecting means, in which, during a normal operation, a fault forcibly generating circuit lets a transmission path signal inputted from the outside pass through as it is, generates a test signal which is the same as that of the transmission path signal, and outputs it to a fault detecting circuit. During a time of testing, the fault forcibly generating circuit outputs "Low" level of the test signal forcibly to the fault detecting circuit, according to a test control signal outputted from a control portion. When the fault detecting circuit detects this test signal, an step-out alarm is generated and transmitted to the control portion. The control portion monitors the step-out alarm from the fault detecting circuit. The control portion judges the operation to be normal if the step-out alarm is outputted, and to be abnormal if the step-out alarm is not outputted under the condition that the step-out alarm is not outputted at the time of non-testing.

Abstract: Methods for testing interconnections on an electronic assembly include the steps of dynamically generating an interconnect topology model from one system, generating test patterns to test the interconnections, applying the test patterns to the boundary scan cells of the system under test to test the interconnections, and determining whether the interconnections match the interconnect topology model. The invention thus dynamically generates an interconnect topology model from a known working system, rather than deriving the interconnect topology model from design data that describes all the interconnections on an electronic assembly.

Abstract: A system and method for automatically detecting the presence and configuration (e.g., number of rows and columns) of a writable memory module. A first data pattern is written to a first memory location. One or more data patterns different from the first data pattern are written to a second and subsequent memory locations in a walking-one sequence. After each write to the second and subsequent memory locations the data pattern at the first memory location is read. The read data pattern is compared to the first data pattern to determine if the first data pattern has been overwritten. The first data pattern is overwritten when the number of memory locations has been exceeded.

Abstract: A semiconductor test system facilitates failure analysis of memory devices by being able to switch one situation where expected data used for an address fail memory is the same as data showing charge/discharge states in the memory cells of a memory device under test and another situation where the expected data is the same as data showing the expected output data of the device under test. For doing this, the semiconductor test system includes a prohibit means 7 for prohibiting the output of the an area inversion memory 22 from transferring to later stages, and an exclusive OR gate 6 which receives an output of the prohibit means 7 at one input and an output of an exclusive OR gate 23 at another input. The exclusive OR gate 6 supplies a resulted output to an address fail memory 5.

Abstract: An integrated circuit includes a circuit architecture that enhances the I.sub.DDQ testability of circuitry such as random access memories. Increased accuracy and test speed are achieved by partitioning the circuit array into multiple partitions. Pairs of partitions connected to a voltage source node and having substantially identical ground line capacitances are subdivided into respective blocks. Each block in a pair of the partitions includes a corresponding block in the other partition. Each of the corresponding blocks in a pair has a substantially equal ground line capacitance, and preferably each of the blocks has a substantially equal ground line capacitance. Pairs of corresponding blocks are coupled to respective built-in current comparators. Each block is preferably configured to include portions of non-contiguous, interleaved bit line segments and portions of non-contiguous, interleaved word lines.

Abstract: A position measuring system for increasing operational dependability, wherein the absolute position is generated by scanning a chain code and erroneously scanned code words are detected and excluded from further processing. A plurality of codes are scanned at areas of the code track which are distanced from each other and are supplied to an error check device.

Abstract: A testable electronic system includes testable elements having standardized test interfaces for organizing the elements in chains which behave like shift registers to ensure the exchange of test information. Each element are either a component including an identifier characterizing the behavior of the test of the component and accessible by the test interface of the component, or a switch for organizing a chain in sub-chains which can be individually selected through channels of the switch. The system includes master switches which define respective sub-sets of elements, a specific channel of each master switch being reserved to access an identifier characterizing the test organization of the associated sub-set.

Abstract: A boundary scan testing device is presented which does not provide a boundary scan test vector generating function for producing boundary scan test vectors corresponding to the boundary scan device under test. Instead, the boundary scan testing device operates based on test vectors produced elsewhere.

Abstract: A dynamic scannable latch circuit for high-speed memory arrays utilized in high-performance integrated circuit devices, wherein the high-speed memory arrays include data-bearing bitlines. The dynamic scannable latch circuit includes a group of scannable latch circuits for serially reading data from high-speed memory arrays during memory-testing cycles wherein each scannable latch circuit provides a scan output to a scan input of a second or next scannable latch circuit in a series of scannable latch circuits. In addition, the dynamic scannable latch circuit includes sensing and combination circuits for sensing the presence of the data-bearing bitlines and for combining the data-bearing bitlines into a memory array output wherein the sensing and combination circuits are coupled to the group of scannable latch circuits. In addition, the sensing and combination circuits further include NAND circuits integrated into a front end of the dynamic scannable latch circuit.

Abstract: A pattern generator that makes it possible to use various option pattern generators (PGs) without changing hardware is realized. To accomplish this, an option circuit includes an option PG initial clock control section that generates an initial clock signal in synchronism with a clock signal to initialize the option PGs; a plurality of option PGs selectively receive one of a plurality of clock output signals of a clock output control section and generate pattern and clock signals; and in a multiplexer which selects one of output signals from the plurality of PGs through an instruction from a select register 24, and a FIFO section which receives a signal from the multiplexer as write data and a write clock, and an output signal of a read clock control section as a read clock, and outputs a signal to a logic circuit as the option PG output signal.

Abstract: The apparatus and method are employed in a communications system has a transmitter and a receiver, where the receiver determines at which of several rates individual frames in a signal have been transmitted by the transmitter. For example, if the transmitter employs four transmission rates, the receiver decodes each frame of the received signal based on the four rates to produce four cyclic redundancy check (CRC) bits, four symbol error rate (SER) values and one or more Yamamoto check values. If only two of the CRC bits check, then the receiver compares to each other the SER values for those two rates to determine at which of the two rates a current frame was transmitted. If only one of the CRC bits check for a given rate, then the SER value for that rate is compared with a maximum SER threshold for that rate. Additionally, SER values for the other rates can be compared to minimum SER thresholds.

Abstract: An electronic device and method for utilizing two extra microcode instructions to generate a set of test patterns which provide complete bitwise self-testing of the on-chip memory of a microcode sequencer. The self-testing sequence can be triggered by a single external interface event.

Abstract: The invention relates to the provision of software with fault tolerant capabilities enabling computer networks to survive or tolerate most individual failures, short of system wide catastrophes such as earthquakes, without loss of data and without loss of access to working data.

Abstract: A processing unit having a CPU core, an integrated RAM and a test unit, which may be implemented in either a test unit, which may be implemented in either hardware or software. A built-in self-test of the RAM is designed to run concurrently with the functional vectors used to test the CPU core. Once the core tests have been activated, a control register may be written to by which will activate the built-in self-test. Thus, the BIST and core testing may overlap to minimize test time.

Abstract: A method and apparatus for producing self-diagnostic information from a circuit board. A circuit board is provided with an on-board processor, an on-board ROM containing diagnostic test software, a frequency generator adapted to produce an electrical signal having a predetermined frequency when an unacceptable response is determined, wherein the predetermined frequency corresponds substantially to the event within the diagnostic test sequence of a particular test for which an unacceptable response is determined. The signal is presented at an output terminal of the circuit board. The status of the circuit board is determined by measuring the frequency of the signal at the output terminal and comparing that frequency to an index of corresponding defects.