Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

Abstract: Provided is a display device. The display device comprises a first substrate, a barrier layer disposed on the first substrate and having amorphous carbon, a first pad part disposed on the barrier layer, a second substrate disposed on the first pad part, a display layer disposed on the second substrate, and a second pad part disposed on a bottom surface of the first substrate and inserted into a first contact hole formed in the first substrate and the barrier layer.

Abstract: A method of fabricating a display panel may include forming an oxide semiconductor pattern on a base layer including a first region and a second region, etching first, second, and third insulating layers to form a first groove that overlaps the second region, forming electrodes on the third insulating layer, forming a fourth insulating layer on the third insulating layer to cover the electrodes, thermally treating the fourth insulating layer, forming an organic layer to cover the fourth insulating layer, and forming an organic light emitting diode on the organic layer.

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

Abstract: A display device including a substrate, a first upper power line, a conductive member, a protective insulating layer, an upper connection member, and a sub-pixel structure. The upper connection member is disposed in a first pad area and a first peripheral area on a planarization layer, and electrically connects the first upper power line and the conductive member through a first contact hole, which is formed in the protective insulating layer and the planarization layer located on the conductive member, and a second contact hole, which is formed in the protective insulating layer and the planarization layer located on the first upper power line.

Abstract: A photodiode-based detection module may include at least one photodiode for detecting light. The photodiode-based detection module may also include a sensitivity damper configured to temporarily reduce the sensitivity of the at least one photodiode. The photodiode-based detection module may further include a controller configured to trigger the sensitivity damper to reduce a sensitivity of the at least one photodiode to less than a nominal sensitivity threshold.

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

Abstract: A support device includes a substrate receiving region. The support device includes a support body shaped as a pattern having an array of openings. The support body is a sparse structure wherein a joint area of the openings of the array of openings is 40% or more of the area of the substrate receiving region. The support body includes one or more suction openings configured to be in fluid communication with a vacuum source arrangement.

Abstract: A display device includes a substrate including a display area provided with pixels disposed therein and a non-display area surrounding the display area and provided with a dummy pattern disposed therein; a light emitting layer formed on the pixels and the dummy pattern; and a bank surrounding the light emitting layer, wherein the dummy pattern includes: a first dummy part extending along a horizontal direction; a second dummy part extending along a vertical direction; and a third dummy part provided by extending the first dummy part and the second dummy part in a corner area where the first dummy part and the second dummy part are connected to each other and having a pattern protruding in an outer direction of the substrate.

Abstract: An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.

Abstract: A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.

Abstract: A display device includes: a substrate; a transistor disposed on the substrate; a first electrode connected to the transistor; an emission layer disposed on the first electrode; a second electrode disposed on the emission layer; a common voltage line connected to the second electrode; and a third electrode and a fourth electrode disposed between the common voltage line and the second electrode.

Abstract: A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

Abstract: A display device including a substrate, a first upper power line, a conductive member, a protective insulating layer, an upper connection member, and a sub-pixel structure. The upper connection member is disposed in a first pad area and a first peripheral area on a planarization layer, and electrically connects the first upper power line and the conductive member through a first contact hole, which is formed in the protective insulating layer and the planarization layer located on the conductive member, and a second contact hole, which is formed in the protective insulating layer and the planarization layer located on the first upper power line.

Abstract: A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

Abstract: Disclosed in the present disclosure are a display device and a display apparatus. The display device includes: a first substrate and a second substrate opposite to the first substrate, a light-emitting pixel array between the first substrate and the second substrate, a reflective plate at a backlight side of the light-emitting pixel array, and a polarization conversion structure and a polarization filtering structure which are successively arranged at a light emission side of the light-emitting pixel array; the polarization filtering structure is for filtering light emitted from the light-emitting pixel array side to the polarization filtering structure, so that target polarized light is transmitted, and non-target deflected light is reflected back; and the polarization conversion structure is for converting transmitted circularly polarized light into linearly polarized light, or converting transmitted linearly polarized light into circularly polarized light.

Abstract: A display substrate includes a first display region and a second display region. The display substrate may include: a first base substrate; a second base substrate; a first barrier layer and a light emitting unit. The first base substrate includes a first through region penetrating the first base substrate, and the first barrier layer includes a second through region penetrating the first barrier layer. The second base substrate includes a first substrate sub-portion located in the first display region, the first substrate sub-portion penetrates the second through region, and at least a portion of the first substrate sub-portion is located in the first through region. The display substrate includes a recessed portion. The second base substrate includes a first surface located in the first display region and a second surface located in the second display region, and the first surface and the second surface are formed as a flat surface.

Abstract: There is provided a package substrate and a semiconductor structure with the same. The package substrate includes a body and a plurality of conducive bridges. The body includes an opening region. The plurality of conductive bridges are disposed separately in the opening region, and adjacent conductive bridges have a respective distance value. At least two of the distance values are not equal.

Abstract: A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.