Patents Examined by Vu A Vu
  • Patent number: 12685179
    Abstract: In an embodiment, a semiconductor package is provided that includes a first package surface and a second package surface opposing the first surface, a plastic molding and one or more semiconductor dies. The first package surface includes a first surface of the plastic molding and a first metallic area exposed from the plastic molding. The first metallic area includes a first product marking including at least one alphanumeric character and the first surface of the plastic molding includes a second product marking including at least one alphanumeric character.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: July 14, 2026
    Assignee: Infineon Technologies Austria AG
    Inventors: Hwee Yin Low, Badrus Hisham Abdul Rani, Wee Aun Jason Lim, Ai Yun Loh, Muhamad Hairul Fauzi Wahid
  • Patent number: 12684691
    Abstract: What is disclosed is a method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.
    Type: Grant
    Filed: July 17, 2024
    Date of Patent: July 14, 2026
    Assignee: VueReal Inc.
    Inventor: Gholamreza Chaji
  • Patent number: 12684775
    Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a stack structure including interlayer insulating layers and conductive layers, which are alternately stacked therein; and a plurality of contact plugs formed vertically on the conductive layers. The stack structure is configured to have a stepped structure, and each of a plurality of steps included in the stepped structure includes at least two interlayer insulating layers, among the interlayer insulating layers, and at least two conductive layers, among the conductive layers. The plurality of contact plugs include at least two contact plugs respectively connected to the at least two conductive layers included in each of the plurality of steps.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: July 14, 2026
    Assignee: SK hynix Inc.
    Inventor: Jae Taek Kim
  • Patent number: 12685088
    Abstract: An apparatus for transferring a semiconductor die from an arrangement dies to a target is provided and relates to a wafer stage, and film frame carrier, and to an assembly including the film frame carrier and arrangement of dies. The wafer chuck includes a rotationally mounted curved shell on which the arrangement of semiconductor dies can be arranged. The wafer stage includes a motor for rotating the curved shell around a rotational axis. The configuration allows improved throughput of the wafer stage. The carrier used with this wafer stage includes a ring-shaped body with an asymmetric bending stiffness allowing the ring-shaped body to be bent so that the mounting surface of the ring-shaped body changes from a first shape to a second more concave shape and prevents or limits the ring-shaped body to be bent so that the mounting surface becomes more convex than the first shape.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: July 14, 2026
    Assignee: Nexperia B.V.
    Inventors: Joep Stokkermans, Gijs van der Veen, Jasper Wesselingh, Patrick Houben
  • Patent number: 12677615
    Abstract: Disclosed is a method for processing a device wafer, in which a device layer, the device layer constituting devices, is stacked on a base material and the devices are formed, respectively, in regions defined by a plurality of intersecting streets on a front surface of the base material. The method includes a first step of dividing the device layer along the streets, a second step of dividing the base material by plasma etching along the streets, and a third step of, before performing at least the second step, forming half-cut grooves by a cutting blade or a laser beam in the base material along the streets, respectively, from a side of a front surface or a side of a back surface of the device wafer. The third and second steps are performed from the side of the same surface of the device wafer.
    Type: Grant
    Filed: August 28, 2023
    Date of Patent: July 7, 2026
    Assignee: DISCO CORPORATION
    Inventor: Naoko Yamamoto
  • Patent number: 12672562
    Abstract: A glass core with a cavity-less local interconnect component architecture for complex multi-die packages. The apparatus has the local interconnect component attached directly to a planar glass layer and surrounded by mold. One or more redistribution layers may be located above and below the apparatus.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: June 30, 2026
    Assignee: Intel Corporation
    Inventors: Jeremy D. Ecton, Hiroki Tanaka, Brandon Christian Marin, Srinivas V. Pietambaram, Suddhasattwa Nad
  • Patent number: 12666620
    Abstract: A semiconductor device may include: a plurality of word lines; a select line; a channel layer extending into the select line through the word lines; a floating gate surrounding sidewalls of the channel layer between the channel layer and the select line; and a charge trap layer including a first and a second portion, wherein the first portion surrounds the sidewalls of the channel layer between the channel layer and the word lines and the second portion surrounds the floating gate between the channel layer and the select line.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: June 23, 2026
    Assignee: SK hynix Inc.
    Inventors: Seok Min Choi, Jung Shik Jang
  • Patent number: 12666921
    Abstract: A processing apparatus using laser according to an embodiment includes a stage configured to hold a substrate and rotate, and a laser irradiation apparatus capable of moving in a radial direction of the rotation. The laser irradiation apparatus includes a control unit configured to control an output of an infrared pulsed laser so that L1/L2 satisfies 1.2 or more and 10 or less when a distance between laser spots adjacent to each other in a rotation direction of the stage is L1 and a distance between laser spots adjacent to each other in the radial direction of the rotation is L2.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: June 23, 2026
    Assignee: Kioxia Corporation
    Inventors: Takuro Okubo, Hidekazu Hayashi
  • Patent number: 12666922
    Abstract: An apparatus for fabricating a display panel and a fabricating method of a display panel are provided. An apparatus for fabricating a display panel includes a loading module of a large-area fabricating substrate fabricated and separated into a plurality of display panels, a solvent application module configured to apply a metal bonding solvent onto the large-area fabricating substrate, and an element transfer module configured to transfer a plurality of light emitting elements or at least one integrated circuit onto the large-area fabricating substrate on which the metal bonding solvent is applied, and the loading module includes a groove type discharge path through which the metal bonding solvent applied by the solvent application module flows and is discharged.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: June 23, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae Hee Lee, Min Woo Kim, Sung Kook Park, Jae Gwang Um
  • Patent number: 12660723
    Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: June 16, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Lim Suk, Dongkyu Kim, Ji Hwang Kim, Hyeonjeong Hwang
  • Patent number: 12660502
    Abstract: The present disclosure relates to a plurality of host materials, an organic electroluminescent compound, and an organic electroluminescent device comprising the same. By comprising a specific combination of host compounds and/or an organic electroluminescent compound according to the present disclosure as an organic electroluminescent material, an organic electroluminescent device having low driving voltage and/or high luminous efficiency and/or long lifespan characteristics can be provided.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: June 16, 2026
    Assignee: DuPont Specialty Materials Korea Ltd.
    Inventors: Ji-Song Jun, Hong-Se Oh, Dong-Hyung Lee, Sang-Hee Cho, Du-Yong Park, Hyun-Woo Kang, Jin-Man Kim
  • Patent number: 12653039
    Abstract: A semiconductor device includes a first die. The first die includes a first dielectric bonding layer thereon and a plurality of first dielectric bonding patterns in the first dielectric bonding layer. A composition of the first dielectric bonding patterns is different from a composition of the first dielectric bonding layer.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: June 9, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Ming-Tsu Chung, Yan-Zuo Tsai
  • Patent number: 12653068
    Abstract: A method for producing a light emitting diode supply substrate for transferring a plurality of light emitting diodes to a supply destination, including: a first mounting step of mounting a plurality of light emitting diodes on a supply substrate; a selective removal step of selectively removing defective light emitting diodes on the supply substrate, and a second mounting step of transferring a normal light emitting diode to a position where the defective light emitting diode has been arranged on the supply substrate. Thus, a method produces a light emitting diode supply substrate capable of producing a light emitting diode supply substrate capable of transferring a plurality of normal light emitting diodes to a supply destination.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: June 9, 2026
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hideo Nakagawa, Yoshinori Ogawa, Nobuaki Matsumoto, Kazunori Kondo
  • Patent number: 12652995
    Abstract: A method of manufacturing a semiconductor device in a semiconductor body is proposed. The method includes processing a semiconductor body at a first surface of the semiconductor body. The method further includes attaching the semiconductor body to a carrier via the first surface. The carrier includes an inner part and an outer part at least partly surrounding the inner part. The method further includes processing the semiconductor body at a second surface opposite to the first surface. The method further includes detaching the inner part of the carrier from the semiconductor body.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 9, 2026
    Assignee: Infineon Technologies AG
    Inventors: Gregor Langer, Bernhard Goller, Nilesha Mishra, Matteo Piccin, Franz-Josef Pichler
  • Patent number: 12648475
    Abstract: A manufacturing method of a structure intended for assembly with another structure by self-aligning bonding by hydrophilic contrast, including the following successive steps: a) definition of pads on the side of the first face of a first substrate; b) transfer of a second substrate on the side of the first face of the first substrate; c) formation on the sides and/or on a peripheral part of the upper face of the pads, of a material more hydrophobic than a material of the upper face of the pads; and d) removal of the second substrate.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: June 2, 2026
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Pierre Montmeat, Frank Fournel, Thierry Enot
  • Patent number: 12648320
    Abstract: A display device is provided. The display device includes a display region which includes a first display region and a second display region, where the first display region includes a plurality of first pixels, and the second display region includes a plurality of second pixels and at least one light transmission region, where the light transmission region has light transmittance that is higher than light transmittance of the first pixel and light transmittance of the second pixel, and the second display region has light transmittance that is higher than light transmittance of the first display region.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: June 2, 2026
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Won Baek, Sang Min Yi, Sang Shin Lee, Sung Chul Kim, Joon Young Park
  • Patent number: 12648219
    Abstract: A semiconductor structure includes fins protruding from a substrate and separated by a dielectric layer, each semiconductor fin including a plurality of semiconductor layers, source/drain (S/D) features disposed in the semiconductor fins, a first metal gate stack and a second metal gate stack disposed over the semiconductor fins and adjacent to the S/D features, where the first and the second metal gate stacks each include a top portion and a bottom portion disposed below the top portion, and where the bottom portion is interleaved with the semiconductor layers, and an isolation feature disposed on the dielectric layer and in contact with a sidewall surface of each of the first and the second metal gate stacks, where the isolation feature protrudes from the top portion of the first and the second metal gate stack, and where the isolation feature includes two compositionally different dielectric layers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 2, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ta Yu, Jiun-Ming Kuo, Yuan-Ching Peng
  • Patent number: 12642051
    Abstract: A first carrier has a first plate. A tape is disposed on the first plate. A second plate is disposed over the first plate. The second plate has a trench aligned to the tape and an opening formed through the second plate over the tape. A singulated semiconductor package is disposed on the tape in the opening of the second plate. A second carrier has a static datum and a movable datum. The movable datum is moved toward the static datum. An aperture substrate is disposed around the static datum and movable datum. A manufacturing process is performed on the aperture substrate.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: May 26, 2026
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Roel Adeva Robles, Chee Kay Chow
  • Patent number: 12635470
    Abstract: A method for making semiconductor devices includes: attaching a substrate with a plurality of electronic components onto a composite tape having an adhesive layer which is sensitive to ultraviolet (UV) irradiation and a UV-transparent base film, wherein the substrate is attached onto the adhesive layer of the composite tape; placing the substrate and the composite tape on a UV-transparent carrier, wherein the UV-transparent carrier is in contact with the UV-transparent base film of the composite tape; singulating the substrate into a plurality of semiconductor devices each having one of the plurality of electronic components; depositing a shielding material on the plurality of semiconductor devices to form a shielding layer on each of the plurality of semiconductor devices; irradiating a UV light to the composite tape through the UV-transparent carrier to reduce adhesivity of the adhesive layer; and detaching the plurality of semiconductor devices from the UV-transparent carrier.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: May 19, 2026
    Inventors: GunHyuck Lee, Yujeong Jang
  • Patent number: 12635236
    Abstract: A stacked FET architecture includes isolated pockets for replacement metal gates for top and bottom nanosheet field-effect transistors. Different work function metals are employed for the metal gates of n-type and p-type FETs. The architecture allows flexibility in providing electrically connected or unconnected metal gates.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: May 19, 2026
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Tenko Yamashita