Patents Examined by Vu A Vu
  • Patent number: 11319458
    Abstract: A protective composition contains a water-soluble polyester resin including a polyvalent carboxylic acid residue and a polyvalent alcohol residue. The polyvalent carboxylic acid residue includes: a polyvalent carboxylic acid residue having a metal sulfonate group; and a naphthalene dicarboxylic acid residue. The proportion of the polyvalent carboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 25 mol % to 70 mol %. The proportion of the naphthalene dicarboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 30 mol % to 75 mol %.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: May 3, 2022
    Assignees: GOO CHEMICAL CO., LTD., PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Teru Sakakibara, Shinya Komabiki, Koji Maeda, Hidehiko Karasaki
  • Patent number: 11315862
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
  • Patent number: 11315881
    Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: April 26, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Chee-Key Chung
  • Patent number: 11316249
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate having a first surface and a second surface opposite to the first surface, an antenna module disposed on the first surface of the first substrate, an electronic component module disposed on the first surface of the first substrate, and a first package body encapsulating the antenna module and the electronic component module. The antenna module has a first surface facing the first surface of the first substrate, a second surface opposite to the first surface of the antenna module, and a lateral surface extending between the first surface of the antenna module and the second surface of the antenna module. The lateral surface of the antenna module faces the electronic component module. A method of manufacturing a semiconductor device package is also provided.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hung-Hsiang Cheng
  • Patent number: 11315951
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate having a first region and a second region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a barrier layer disposed on the semiconductor layer, a first source electrode, a first drain electrode, and a first gate electrode disposed therebetween, which are disposed on the barrier layer in the first region, a second source electrode, a second drain electrode, and a second gate electrode disposed therebetween, which are disposed on the barrier layer in the second region, and a ferroelectric pattern interposed between the first gate electrode and the barrier layer.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: April 26, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Jae Chang, Dong Min Kang, Sung-Bum Bae, Hyung Sup Yoon, Kyu Jun Cho
  • Patent number: 11302562
    Abstract: The present disclosure provides a method and an apparatus for mass transfer of Micro LEDs. In one embodiment, the method comprises: providing Micro LED chips; dumping at one time Micro LED chips onto a transfer surface of a transfer mold, the transfer surface being formed with transfer cavities; and vibrating the transfer mold to cause the Micro LED chips to fall into shape-matched transfer cavities respectively, and tilting the transfer mold so that the Micro LED chips that have not fallen into the transfer cavities leave the transfer surface.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: April 12, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Guohua Wang
  • Patent number: 11302563
    Abstract: A carrier assembly is configured to support a wafer, including during back end of line (BEOL) processing. The carrier assembly includes dual carriers. A first carrier includes a stepped structure so as to situate the wafer. A side of the wafer is bonded to the first carrier without adhesive. The first carrier is positioned atop the second carrier, so as to be mechanically supported by the second carrier. Each carrier is made by wet etching of laminated glass, without mechanical polishing.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 12, 2022
    Assignee: CORNING INCORPORATED
    Inventors: Hoon Kim, Jin Su Kim, Varun Singh
  • Patent number: 11295953
    Abstract: An apparatus for micromachining a semiconductor material from opposing sides through synchronous coordination of laser and electrochemistry includes an optical path system, a stable low-pressure jet generation system, and an electrolytic machining system. The optical path system includes a laser generator, a beam expander, a reflector, a galvanometer, and a lens. The electrolytic machining system includes a direct-current pulsed power supply, an adjustable cathode fixture, an electrolyte tank, a current probe, and an oscilloscope. The stable low-pressure jet generation system provides an electrolyte flow into a metal needle. The electrolyte flow forms an electrolyte layer between a semiconductor material and a cathode copper plate, such that the cathode and the anode are in electrical contact with each other. In a method employing the apparatus, a laser beam is irradiated onto the semiconductor material to form a local high-temperature region, which leads to a localized increase in electrical conductivity.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: April 5, 2022
    Assignee: JIANGSU UNIVERSITY
    Inventors: Hao Zhu, Zhi Zhang, Senshan Mao, Shuaijie Zhu, Zhaoyang Zhang, Kun Xu, Anbin Wang, Douyan Zhao
  • Patent number: 11289360
    Abstract: Disclosed are methods and apparatus for protecting dielectric films on microelectronic components from contamination associated with singulation, picking and handling of singulated microelectronic components from a wafer for assembly with other components.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, Brandon P. Wirz, Wei Zhou
  • Patent number: 11289391
    Abstract: A device comprising a semiconductor substrate, an electrically-conductive layer covering the substrate, and an insulating sheath, the conductive layer being in contact with the insulating sheath on the side opposite to the substrate.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 29, 2022
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Olivier Ory
  • Patent number: 11289359
    Abstract: A method of manufacturing a device includes: —a) a first step for the formation of a temporary structure that comprises electroluminescent structures separated by trenches and comprising an electroluminescent face, the electroluminescent structures being bonded by means of a bond layer on a temporary substrate; b) an assembly step bringing the electroluminescent structures into contact with a host face of a host substrate; and c) a step for removal of the temporary substrate; wherein the bond layer, that comprises an electrically conducting organic polymer material at least partially transparent to light radiation, is at least partly kept after step c) and forms an electrode common to the light emitting faces, with a thickness of more than 20 nm.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 29, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Bertrand Chambion
  • Patent number: 11289468
    Abstract: A package structure includes an inner wiring layer, a first dielectric layer, a first outer wiring layer, and an electronic component assembly. The first dielectric layer includes a first surface and a second surface facing away from the first surface. The inner wiring layer and the electronic component assembly are embedded into the first dielectric layer from the first surface. The first outer wiring layer is disposed on the second surface. The electronic component assembly includes a first electronic element and a second electronic element. The second electronic element is disposed close to the second surface, and an electrical connector of the second electronic element faces the second surface. The first electronic element is disposed on a side of the second electronic element facing away from the second surface, and exposed from the first surface. The first outer wiring layer electrically connects the electrical connector of the second electronic element and the inner wiring layer, respectively.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 29, 2022
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Patent number: 11289387
    Abstract: Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 29, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prayudi Lianto, Sik Hin Chi, Shih-Chao Hung, Pin Gian Gan, Ricardo Fujii Vinluan, Gaurav Mehta, Ramesh Chidambaram, Guan Huei See, Arvind Sundarrajan, Upendra V. Ummethala, Wei Hao Kew, Muhammad Adli Danish Bin Abdullah, Michael Charles Kutney, Mark McTaggart Wylie, Amulya Ligorio Athayde, Glen T. Mori
  • Patent number: 11282746
    Abstract: A method of manufacturing a microelectronic device may include forming a wiring layer on a first surface of a wafer. The method may also include forming a modified layer along separation regions for each microelectronic device of the wafer by focusing a laser on an inside portion of the wafer. The method may also include removing material from the second surface of the wafer. The wafer may be cooled to a temperature where a low dielectric constant layer extending across the separation regions is brittle while the material is removed from the second surface of the wafer. The method may further include separating the wafer along the separation region to form separate microelectronic devices.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Suresh K. Upadhyayula, Thiam Chye Lim
  • Patent number: 11276603
    Abstract: A transfer method of transferring an object to a target substrate by using a deformable film is provided. The method includes: a first process of forming an object on a source substrate, a second process of placing a deformable film on the source substrate on which the object is formed, a third process of embedding the object into the deformable film, a fourth process of separating an object, which is to be transferred, from the source substrate, integrating the transfer object in or on a surface of the deformable film, and separating deformable film, in which the transfer object is integrated, from the source substrate, and a fifth process of transferring the object integrated into the deformable film to a target substrate.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: March 15, 2022
    Assignee: LC SQUARE CO., LTD.
    Inventors: Je Hyuk Choi, Chang Wan Kim, Chan Soo Shin, Hyeong Ho Park, Shin Keun Kim
  • Patent number: 11264310
    Abstract: A method includes attaching semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing the semiconductor dies of the respective columns in respective first and second package structures; trimming the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving the first columns along a column direction relative to the second columns; and separating individual packaged electronic devices of the respective first and second columns from one another.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: March 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng Eugene Lee, Anis Fauzi Bin Abdul Aziz, Sueann Wei Fen Lim, Jin Keong Lim
  • Patent number: 11264280
    Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 1, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Kazunori Fuji
  • Patent number: 11264356
    Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Andreas Grassmann, Martin Gruber, Thorsten Scharf
  • Patent number: 11264531
    Abstract: A micro light emitting diode (LED) transfer device includes a transfer part configured to transfer a plurality of LEDs arranged on a first substrate to a relay substrate; a memory configured to store characteristic information of each of the plurality of LEDs; and a processor configured to determine arrangement locations of each of the plurality of LEDs on the relay substrate based on the stored characteristic information, and control the transfer part to transfer the plurality of LEDs to the determined arrangement locations.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangmoo Park, Doyoung Kwag, Eunhye Kim, Minsub Oh, Yoonsuk Lee
  • Patent number: 11264279
    Abstract: Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 1, 2022
    Assignee: NEXT Biometrics Group ASA
    Inventors: Tian Xiao, King Hong Kwan, Sheng-Hsiang Hung, Mark W. Naumann