Abstract: A semiconductor structure includes a wafer circuit structure, at least one first semiconductor die, at least one first supporting structure, and an encapsulant. The at least one first semiconductor die is disposed over and electrically connected to the wafer circuit structure in a device region of the semiconductor structure. The at least one first supporting structure is disposed over the wafer circuit structure in a peripheral region of the semiconductor structure. The encapsulant is disposed over the wafer circuit structure and encapsulates the at least one first semiconductor die and the at least one first supporting structure, where a thickness of the encapsulant at an edge of the semiconductor structure is less than a thickness of the encapsulant within the device region of the semiconductor structure.

Abstract: An image sensor includes a sensor substrate includes first, second, and third pixels respectively sensing first, second and third wavelengths of light, A color separating lens array changes phase of light of the first, second, and third wavelengths, and condenses the phase-changed light onto the first, second and third pixels, respectively. The color separating lens array includes first to third pixel corresponding regions respectively facing the first to third pixels. The first pixel corresponding region includes a plurality of first nanoposts, the second pixel corresponding region includes a plurality of second nanoposts, and the third pixel corresponding region includes a plurality of third nanoposts, a second center nanopost having a greatest cross-sectional width among the second nanoposts overlaps a center of the second pixel, and a third center nanopost having a greatest cross-sectional width among the third nanoposts does not overlap a center of the third pixel.

Abstract: A method for manufacturing a semiconductor device includes preparing a plurality of semiconductor elements, preparing a support member, attaching the plurality of semiconductor elements to the support member so that second surfaces of the plurality of semiconductor elements face the support member, encapsulating the plurality of semiconductor elements with an encapsulation material, removing the support member from an encapsulation material layer in which the plurality of semiconductor elements is encapsulated with the encapsulation material, bonding a first protective film to a second surface of the encapsulation material layer located on the second surface side of the plurality of semiconductor elements, and forming a re-distribution layer on a first surface of the encapsulation material layer located on the first surface side of the plurality of semiconductor elements after bonding the first protective film to the encapsulation material layer.

Abstract: Provided is a test method including: placing, on a placement unit, a panel level package in which a plurality of unsingulated devices are formed in a matrix; bringing a plurality of contacts electrically connected to a plurality of terminals of a test circuit into contact with a plurality of contact terminals provided on one side in the panel level package in a row direction of the matrix and connected via a plurality of lead-out wirings to an internal circuit of each device in each row of the plurality of devices, respectively; and testing, by the test circuit, each device in the each row electrically connected via the plurality of contacts.

Abstract: A manufacturing method of a semiconductor structure including the following steps is disclosed. A definition layer is formed on a substrate. The definition layer includes a first dielectric layer and a second dielectric layer. A first isotropic etching process is performed on the second dielectric layer to form a first opening in the second dielectric layer. A portion of the first opening is located under the patterned photoresist layer. A first anisotropic etching process is performed on the first dielectric layer to form a second opening in the first dielectric layer. The first opening is connected to the second opening to form a third opening. The patterned photoresist layer is removed. An etch back process is performed on the first dielectric layer and the second dielectric layer, so that a sidewall of the definition layer exposed by the third opening is an inclined surface.

Abstract: A highly reliable display apparatus is provided at a low cost. The display apparatus includes a light-emitting diode included in a pixel circuit, a transistor included in the pixel circuit, and a transistor included in a driver circuit of the pixel circuit, which are stacked to have an overlap region. With such a structure, the display apparatus can be downsized. In addition, in the display apparatus, a plurality of light-emitting diodes can be attached to a circuit board formed with a transistor and the like in one step. Consequently, the manufacturing cost of the display apparatus can be reduced.

Abstract: A chip bonding system (1) includes a dicing device (20) to, by dicing a dicing substrate stuck on a sheet (TE), generate a plurality of chips (CP) stuck on the sheet (TE) with chips (CP) adjacent to each other joined to each other via remaining uncut portions, an activation treatment device (60) to activate bonding surfaces of respective ones of the chips (CP) stuck to the sheet (TE), a sheet stretching device (40) to, by stretching the sheet (TE) on which the chips (CP) having bonding surfaces activated by the activation treatment device (60) are stuck, brings the chips (CP) into a state of being separated from one another, and a bonding device (30) to, by bringing one chip (CP) picked out of the chips (CP) separated from one another into contact with a substrate (WT), bond the one chip (CP) to the substrate (WT).

Abstract: A component manufacturing method includes: a step of arranging a plurality of electronic components in a state where electrodes are exposed, on a support having a substrate and a holding layer, with the holding layer interposed therebetween; and a step of evaluating electric characteristics of 80 or more of the electronic components among the electronic components arranged on the support by bringing all or some of the exposed electrodes and probes into contact with each other and simultaneously performing conduction evaluation. A component manufacturing film includes a resin base layer, the holding layer provided on one surface side of the resin base layer, and a joint layer that is provided on an opposite side of the resin base layer and bonds the component manufacturing film to the substrate. A component manufacturing tool includes the substrate and the holding layer provided to one surface of the substrate.

Abstract: An example semiconductor package includes a semiconductor die. In addition, the semiconductor package includes a mold compound having a first side, a second side opposite the first side, and an axis extending between the first side and the second side, the mold compound covering the semiconductor die. Further, the semiconductor package includes an interface member including a first portion and a second portion, the first portion is coupled to the second portion. The first portion is positioned along the first side, the second portion is positioned along the second side, and an engagement of a welding horn with the first portion is adapted to weld the second portion to a surface.

Abstract: According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first wafer. The first wafer may include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. A pointing direction of the first mark may be the same as an extending direction of the first dicing lane. A cleavage plane of the first wafer may be parallel to the pointing direction of the first mark. The pointing direction of the first mark may be an extending direction of a line of symmetry of the first wafer. The semiconductor structure may include a second wafer. The second wafer and the first wafer may be disposed in a stack. The second wafer may be a plurality of memory array chips.

Abstract: A semiconductor package with two interposers, and the method of forming the same are provided. The semiconductor package may include a first interposer, a first semiconductor die on the first interposer, a second interposer on the first semiconductor die, and a second semiconductor die on the second interposer. The second interposer may be between the first semiconductor die and the second semiconductor die. The first semiconductor die may be bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding. The second semiconductor die may be bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding.

Abstract: The present disclosure provides a display panel and a display device that include a display area including a first optical area, a first optical bezel area located outside of the first optical area, and a normal area located outside of the first optical bezel area, and a non-display area, wherein each of the first optical area, the first optical bezel area, and the normal area may include two or more light emitting areas among a plurality of light emitting areas, and the first optical area may be a transmittable area. The plurality of light emitting areas may include a first light emitting area included in the first optical area, a second light emitting area emitting light of the same color as the first light emitting area and included in the first optical bezel area, and a third light emitting area emitting light of the same color as the first light emitting area and included in the normal area.

Abstract: A method for producing a semiconductor device, including forming a temporary fixing laminated body including a carrier, and a sealing structure body provided on a main surface of the carrier, and removing the carrier from the temporary fixing laminated body. The temporary fixing laminated body is formed by a method including adhering the curable resin film and the carrier. The carrier is removed from the temporary fixing laminated body by separating a protective layer that is the curable resin film that is cured from the carrier. The curable resin film exhibits a transmittance of 20% or less with respect to light at a wavelength of 355 nm when cured.

Abstract: Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provide a bonded structure with reliable electrical contacts.

Abstract: In an embodiment, a semiconductor package is provided that includes a first package surface and a second package surface opposing the first surface, a plastic molding and one or more semiconductor dies. The first package surface includes a first surface of the plastic molding and a first metallic area exposed from the plastic molding. The first metallic area includes a first product marking including at least one alphanumeric character and the first surface of the plastic molding includes a second product marking including at least one alphanumeric character.

Abstract: What is disclosed is a method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a stack structure including interlayer insulating layers and conductive layers, which are alternately stacked therein; and a plurality of contact plugs formed vertically on the conductive layers. The stack structure is configured to have a stepped structure, and each of a plurality of steps included in the stepped structure includes at least two interlayer insulating layers, among the interlayer insulating layers, and at least two conductive layers, among the conductive layers. The plurality of contact plugs include at least two contact plugs respectively connected to the at least two conductive layers included in each of the plurality of steps.

Abstract: An apparatus for transferring a semiconductor die from an arrangement dies to a target is provided and relates to a wafer stage, and film frame carrier, and to an assembly including the film frame carrier and arrangement of dies. The wafer chuck includes a rotationally mounted curved shell on which the arrangement of semiconductor dies can be arranged. The wafer stage includes a motor for rotating the curved shell around a rotational axis. The configuration allows improved throughput of the wafer stage. The carrier used with this wafer stage includes a ring-shaped body with an asymmetric bending stiffness allowing the ring-shaped body to be bent so that the mounting surface of the ring-shaped body changes from a first shape to a second more concave shape and prevents or limits the ring-shaped body to be bent so that the mounting surface becomes more convex than the first shape.

Abstract: Disclosed is a method for processing a device wafer, in which a device layer, the device layer constituting devices, is stacked on a base material and the devices are formed, respectively, in regions defined by a plurality of intersecting streets on a front surface of the base material. The method includes a first step of dividing the device layer along the streets, a second step of dividing the base material by plasma etching along the streets, and a third step of, before performing at least the second step, forming half-cut grooves by a cutting blade or a laser beam in the base material along the streets, respectively, from a side of a front surface or a side of a back surface of the device wafer. The third and second steps are performed from the side of the same surface of the device wafer.