Abstract: A substrate processing apparatus configured to process a combined substrate in which a first substrate, an interface layer including at least a laser absorbing film, and a second substrate are stacked on top of each other includes a substrate holder configured to hold the combined substrate; an interface laser radiating unit configured to radiate laser light to the laser absorbing film in a pulse shape; a moving mechanism configured to move the substrate holder and the interface laser radiating unit relative to each other; and a controller. The controller performs a control of acquiring information of the interface layer formed in the combined substrate, and a control of setting, based on the acquired information of the interface layer, a bonding interface having a weakest adhesive strength among bonding interfaces in the interface layer as a separation interface between the first substrate and the second substrate.

Abstract: A semiconductor device includes a first stacked field-effect transistor structure having a first lower field-effect transistor device and a first upper field-effect transistor device. The semiconductor device also includes a second stacked field-effect transistor structure comprising a second lower field-effect transistor device and a second upper field-effect transistor device, where at least one of: the first lower field-effect transistor device includes a different number of channel layers than the second lower field-effect transistor device; and the first upper field-effect transistor device includes a different number of channel layers than the second upper field-effect transistor device.

Abstract: The present disclosure provides a semiconductor device based on a dielectric material containing a metal interstitial impurity, including: a substrate, a dielectric material layer, and a functional layer. A material for preparing the dielectric material layer is a compound containing the metal interstitial impurity. The dielectric material layer and/or the functional layer is configured to subject to at least one of electricity, heat, light or magnetism, such that the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state.

Abstract: Provided are a display panel, a preparation method thereof, and a display apparatus. The display panel includes a display region and a fan-out wire region. The display region includes multiple data lines. The fan-out wire region includes multiple fan-out wires. A fan-out wire of the multiple fan-out wires is electrically connected to a respective data line of the multiple data lines. The fan-out wires include multiple first fan-out wires and multiple second fan-out wires. A second fan-out wire is located on a side of a first fan-out wire facing away from a substrate. The first fan-out wire includes a first main portion and a first edge portion. The second fan-out wire includes a second main portion and a second edge portion. At least one first main portion does not overlap at least one second main portion.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a fin-shaped structure on the MOSCAP region, forming a shallow trench isolation (STI) around the substrate and the fin-shaped structure, performing a first etching process to remove part of the STI on the MOSCAP region, and then performing a second etching process to remove part of the STI on the non-MOSCAP region and the MOSCAP region.

Abstract: A display substrate, a display panel and a display device are provided. The display substrate includes: sub-pixels; a first initialization voltage signal line; a first electrode disposed on the base substrate; a pixel defining layer disposed on a side of the first electrode layer away from the base substrate. At least one sub-pixel includes a pixel opening located in the pixel defining layer. The first initialization voltage signal line includes a first sub-line with a main body extending in a first direction and a second sub-line with a main body extending in a second direction. An orthographic projection of one second sub-line on the base substrate is located on a first side of a midpoint of a pixel opening of one first sub-pixel, and an orthographic projection of another second sub-line on the base substrate is located on a second side of a midpoint of a pixel opening of the other first sub-pixel.

Abstract: The present disclosure relates to a tape removing device and a tape removing method. The present disclosure provides a tape removing device comprising: a working table; a suction nozzle; a workpiece for tape removing, the workpiece for tape removing including a support adhesive layer and at least one workpiece bonded to a side of the support adhesive layer, in which one side of the support adhesive layer provided with the at least one workpiece is facing the working table; and a guiding roll in contact with the other side of the support adhesive layer, wherein the suction nozzle fixes the workpiece for tape removing on the working table. Therefore, it is possible to avoid stripping off the support adhesive layer from the workpiece at a right angle, thereby reducing damages to the workpiece, which in turn can reduce the risk of invisible product cracks and improve product reliability.

Abstract: The present disclosure relates to a method of manufacturing a packaging substrate and a packaging substrate manufactured thereby. The method of manufacturing a packaging substrate according to the present disclosure includes: generating a glass structure that is a core via, a cavity portion, or both on a glass core including a first surface and a second surface facing each other; forming an insulating layer on the first surface or second surface using an insulating film; and forming an upper layer including an upper distribution layer and an upper surface connection layer on the insulating layer. The forming of the insulating layer May include a primary curing operation of laminating a first insulating film on the first surface and primarily curing the first insulating film, and a secondary curing operation of laminating a second insulating film on the primarily cured first insulating film and secondarily curing the second insulating film.

Abstract: A semiconductor device includes a first semiconductor chip.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes the following steps. A trench is formed in a first interlayer dielectric (ILD) layer. A metal conductor with metal dopants is filled in the trench. Planarization is performed on the metal conductor with the metal dopants. A thermal treatment, a photo treatment or a bias-assist treatment is performed on the metal conductor with the metal dopants to form a self-forming metal capping layer on a first metal layer. An etching stop bi-layer structure is formed on the first interlayer dielectric layer and the self-forming metal capping layer. A via, a second interlayer dielectric (ILD) layer and a second metal layer are formed on the etching stop bi-layer structure. The via is embedded in the second interlayer dielectric layer and the via is disposed between the first metal layer and the second metal layer.

Abstract: A multi-channel visible light communication system includes a carrier board and a plurality of light-emitting device stacks. The light-emitting device stacks are arranged over the carrier board. Each of the light-emitting device stacks includes a first light-emitting device, a second light-emitting device and a first adhesive layer. The second light-emitting device is disposed over the first light-emitting device. The first adhesive layer is disposed between the first light-emitting device and the second light-emitting device. The first adhesive layer includes a first metasurface. The first metasurface is configured to pass a first color light emitted from the first light-emitting device and reflect a second color light emitted from the second light-emitting device.

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, and a sidewall between the first surface and the second surface. A build-up layer is on at least the first surface. A plurality of regions is on the sidewall. Each region comprises a cavity in the sidewall, wherein the cavity spans a first distance in a first direction from the first surface toward the second surface. In addition, the cavity comprises a concave surface having a first depth at the first surface and a second depth at the first distance, the second depth being less than the first depth.

Abstract: This application is directed to controlling underfill bleed-out in semiconductor packaging. A first substrate is disposed on a support substrate, and a bracket structure is placed on the support substrate with a first separation from the first substrate. An underfill material is applied on the support substrate. The bracket structure automatically controls bleed-out of the underfill material. In some embodiments, in accordance with a determination that the underfill material is substantially hardened, the bracket structure is removed from the support substrate. In some embodiments, the first substrate includes a semiconductor package, and the support substrate includes a printed circuit board (PCB). Alternatively, in some embodiments, the first substrate includes a chip, and the support substrate includes a semiconductor package and forms a system in a package (SiP) with the first substrate.

Abstract: A semiconductor device includes: a 1st source/drain region; a 2nd source/drain region; a channel structure connecting the 1st source/drain region to the 2nd source/drain region; a gate structure configured to control the channel structure; a backside source/drain contact structure connected to a bottom surface of the 1st source/drain region; a backside isolation structure at a lower portion of the semiconductor device; and a 1st contact spacer on the backside source/drain contact structure, wherein the 1st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure.

Abstract: In an aspect, a substrate structure includes plurality of substrates encapsulated in a shell in a stacked relationship; at least one electronic component in each substrate of the plurality of substrates, wherein the at least one electronic component includes at least a first terminal and a second terminal; a first redistribution layer (RDL) disposed over each substrate of the plurality of substrates configured to electrically couple the first terminal of the at least one electronic component with a respective first terminal disposed over an outer edge of the shell; and a second RDL disposed over each substrate of the plurality of substrates and configured to electrically couple the second terminal of the at least one electronic component with a respective second terminal disposed over the outer edge of the shell.

Abstract: A display module includes a substrate, a plurality of pixel units are arrayed on the substrate, and each of the pixel units is provided with at least three light-emitting chips, and the centers of at least three light-emitting chips are not collinear; and the projections of at least three light-emitting chips along a first direction at least partially overlap, and the projections of at least three light-emitting chips along a second direction at least partially overlap where the first direction is perpendicular to the second direction.

Abstract: A semiconductor structure includes a wafer circuit structure, at least one first semiconductor die, at least one first supporting structure, and an encapsulant. The at least one first semiconductor die is disposed over and electrically connected to the wafer circuit structure in a device region of the semiconductor structure. The at least one first supporting structure is disposed over the wafer circuit structure in a peripheral region of the semiconductor structure. The encapsulant is disposed over the wafer circuit structure and encapsulates the at least one first semiconductor die and the at least one first supporting structure, where a thickness of the encapsulant at an edge of the semiconductor structure is less than a thickness of the encapsulant within the device region of the semiconductor structure.

Abstract: An image sensor includes a sensor substrate includes first, second, and third pixels respectively sensing first, second and third wavelengths of light, A color separating lens array changes phase of light of the first, second, and third wavelengths, and condenses the phase-changed light onto the first, second and third pixels, respectively. The color separating lens array includes first to third pixel corresponding regions respectively facing the first to third pixels. The first pixel corresponding region includes a plurality of first nanoposts, the second pixel corresponding region includes a plurality of second nanoposts, and the third pixel corresponding region includes a plurality of third nanoposts, a second center nanopost having a greatest cross-sectional width among the second nanoposts overlaps a center of the second pixel, and a third center nanopost having a greatest cross-sectional width among the third nanoposts does not overlap a center of the third pixel.

Abstract: A method for manufacturing a semiconductor device includes preparing a plurality of semiconductor elements, preparing a support member, attaching the plurality of semiconductor elements to the support member so that second surfaces of the plurality of semiconductor elements face the support member, encapsulating the plurality of semiconductor elements with an encapsulation material, removing the support member from an encapsulation material layer in which the plurality of semiconductor elements is encapsulated with the encapsulation material, bonding a first protective film to a second surface of the encapsulation material layer located on the second surface side of the plurality of semiconductor elements, and forming a re-distribution layer on a first surface of the encapsulation material layer located on the first surface side of the plurality of semiconductor elements after bonding the first protective film to the encapsulation material layer.

Abstract: Provided is a test method including: placing, on a placement unit, a panel level package in which a plurality of unsingulated devices are formed in a matrix; bringing a plurality of contacts electrically connected to a plurality of terminals of a test circuit into contact with a plurality of contact terminals provided on one side in the panel level package in a row direction of the matrix and connected via a plurality of lead-out wirings to an internal circuit of each device in each row of the plurality of devices, respectively; and testing, by the test circuit, each device in the each row electrically connected via the plurality of contacts.