Patents Examined by Vu A Vu
  • Patent number: 12040302
    Abstract: A transistor package having four terminals includes a semiconductor transistor chip and a semiconductor diode chip. The semiconductor transistor chip includes a control electrode and a first load electrode on a first surface and a second load electrode on a second surface opposite the first surface. The semiconductor diode chip includes a first diode electrode on a first surface and a second diode electrode on a second surface opposite the first surface. The transistor package includes a first terminal electrically connected to the control electrode, a second terminal electrically connected to the first diode electrode, a third terminal electrically connected to the first load electrode and a fourth terminal electrically connected to the second load electrode. At least the first terminal, the second terminal and the third terminal protrude from one side of transistor package. The first terminal is arranged between the second terminal and the third terminal.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: July 16, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Hyeongnam Kim, Mohamed Imam
  • Patent number: 12040291
    Abstract: Radio frequency (RF) packages containing multilevel power substrates and associated fabrication methods are disclosed. In an embodiment, the method includes producing a multilevel substrate panel by obtaining a base panel level containing prefabricated base structures and having a surface through which metallic surfaces of the prefabricated base structures are exposed. A secondary panel level is formed on the base layer to include patterned metal features embedded in a secondary dielectric body and electrically contacting the exposed metallic surfaces of the prefabricated base structures at a direct plated interface. The presingulated array of multilevel power substrates is separated into singulated multilevel power substrates each including a base substrate level formed from a singulated piece of the base panel level and a secondary substrate level formed from a singulated piece of the secondary substrate level.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: July 16, 2024
    Assignee: NXP USA, Inc.
    Inventors: Zhiwei Gong, Li Li, Lu Li, Lakshminarayan Viswanathan, Fernando A. Santos, Burton Jesse Carpenter
  • Patent number: 12040593
    Abstract: A multi-wavelength laser is provided, including a reference wavelength-tunable laser, N?1 secondary wavelength-tunable lasers, N beam splitters, a phase modulator, and N?1 frequency difference detection apparatuses. The reference wavelength-tunable laser is connected to one beam splitter which includes two output ports, and one of the output ports is connected to the phase modulator. The phase modulator is separately connected to the N?1 frequency difference detection apparatuses. The N?1 secondary wavelength-tunable lasers one-to-one correspond to remaining N?1 beam splitters and the N?1 frequency difference detection apparatuses. The secondary wavelength-tunable laser is connected to a corresponding beam splitter, the corresponding beam splitter includes two output ports, and one of the output ports is connected to a corresponding frequency difference detection apparatus. N is a positive integer not less than 2.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: July 16, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jialin Zhao, Chengcheng Gui, Shengmeng Fu
  • Patent number: 12031731
    Abstract: A Thermal Performance Forecast approach is described that can be used to forecast heating and cooling fuel consumption based on changes to user preferences and building-specific parameters that include indoor temperature, building insulation, HVAC system efficiency, and internal gains. A simplified version of the Thermal Performance Forecast approach, called the Approximated Thermal Performance Forecast, provides a single equation that accepts two fundamental input parameters and four ratios that express the relationship between the existing and post-change variables for the building properties to estimate future fuel consumption. The Approximated Thermal Performance Forecast approach marginally sacrifices accuracy for a simplified forecast.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: July 9, 2024
    Assignee: CLEAN POWER RESEARCH, L.L.C.
    Inventor: Thomas E. Hoff
  • Patent number: 12034054
    Abstract: A method includes forming a gate dielectric layer and a dummy gate layer; forming a mask over the dummy gate layer; patterning the gate dielectric layer and the dummy gate layer to form a dummy gate structure, the dummy gate structure including a remaining portion of the gate dielectric layer and a remaining portion of the dummy gate layer; epitaxially growing a first spacer layer on the dummy gate structure and the substrate, in which the first spacer layer has a higher growth rate on the exposed surfaces of the dummy gate structure and the substrate than on exposed surfaces of the mask; doping the first spacer layer to form a doped spacer layer having a different lattice constant than the substrate; depositing a second spacer layer over the doped spacer layer; and etching the second spacer layer and the doped spacer layer to form a gate spacer.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chun-Ting Chou
  • Patent number: 12021016
    Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: June 25, 2024
    Assignee: Intel Corporation
    Inventors: Chandra Mohan Jha, Pooya Tadayon, Aastha Uppal, Weihua Tang, Paul Diglio, Xavier Brun
  • Patent number: 12021351
    Abstract: The diode laser comprises a laser bar having a semiconductor body and an active layer, wherein the laser bar has a plurality of individual emitters. At least some individual emitters are respectively assigned a section of the semiconductor body and a current regulating element connected in series therewith, such that, during operation of the individual emitters as intended, an electrical operating current I0 fed to the individual emitter in each case flows completely through the assigned section of the semiconductor body and in the process a voltage drop UH occurs at the section and at least part of said operating current I0 flows through the assigned current regulating element and experiences an electrical resistance RS in the process. In the case of the individual emitters, the current regulating element assigned in each case is configured such that the resistance Rg at an operating temperature T0 has a positive temperature coefficient dRS/dT|T0.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 25, 2024
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Harald König, Bernhard Stojetz, Alfred Lell, Muhammad Ali
  • Patent number: 12021058
    Abstract: A system for connecting electronic assemblies and/or for manufacturing workpieces has a plurality of modules for connecting the electronic assemblies and/or for manufacturing the workpieces. At least one module is a loading station and one is an unloading station, or one module is a loading station and unloading station. At least one further module is a manufacturing station, and a manufacturing workpiece carrier is provided for accommodating the electronic assemblies and/or workpieces which is movable in automated manner by a conveying unit from the loading station via the manufacturing station to the unloading station. A multiple gripper is provided by which at least two electronic assemblies and/or workpieces are simultaneously placeable onto the manufacturing workpiece carrier. A foil/film transfer unit and a foil/film detachment unit and a manufacturing workpiece carrier with at least two workpieces is provided.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 25, 2024
    Assignee: PINK GMBH THERMOSYSTEME
    Inventors: Christoph Oetzel, Stefan Müssig
  • Patent number: 12021346
    Abstract: A multi-module fiber laser capable of monitoring abnormalities of optical modules in real time. In the multi-module fiber laser, the CAN bus is employed to directly obtain whether each of the slave control modules or the master control module is in normal working condition, so that the CAN bus is at the status level corresponding to whether all modules are in normal working state, namely, the CAN bus that is configured to transmit the light control signal issued by the master control module. The status level of the slave control module or the combiner module is also transmitted via the CAN bus, so that all the slave control modules can quickly put themselves in the corresponding working state according to the status level of the CAN bus.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: June 25, 2024
    Assignee: WUHAN RAYCUS FIBER LASER TECHNOLOGIES CO., LTD.
    Inventors: Wei Jiang, Dapeng Yan, Yong Ruan, Jianhong Shi, Lidong Jiang
  • Patent number: 12015003
    Abstract: An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: June 18, 2024
    Assignee: International Business Machines Corporation
    Inventors: John Knickerbocker, Mukta Ghate Farooq, Katsuyuki Sakuma
  • Patent number: 12015242
    Abstract: The optical module which is disclosed in the present application comprises a plate-like metal stem in which a metallic lead pin is inserted in a through-hole so as to be coaxial with the through-hole and one sheet of a dielectric substrate which is equipped with a high-frequency signal line to be connected to the lead pin and a semiconductor optical integrated element, in which a semiconductor laser and an optical modulator are integrated, and which is connected to the high-frequency signal line with a bonding wire, wherein one side surface of the dielectric substrate extends in a direction perpendicular to the light axis direction of the semiconductor optical integrated element, and the side surface of the dielectric substrate is arranged in contact with a surface of the metal stem.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: June 18, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuki Otani, Norio Okada
  • Patent number: 12015247
    Abstract: An optical transmission apparatus includes a first multilevel optical phase modulator and a first semiconductor optical amplifier. The first semiconductor optical amplifier includes a first active region having a first multiple quantum well structure. Assuming that a first number of layers of a plurality of first well layers is defined as n1 and a first length of the first active region is defined as L1 (?m): (a) n1=5 and 400?L1?563; (b) n1=6 and 336?L1?470; (c) n1=7 and 280?L1?432; (d) n1=8 and 252?L1?397; (e) n1=9 and 224?L1?351; or (f) n1=10 and 200?L1?297.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 18, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shusaku Hayashi, Satoshi Nishikawa, Koichi Akiyama
  • Patent number: 12009637
    Abstract: A semiconductor light emitting device of an embodiment of the present disclosure includes: a nitride semiconductor substrate having, as a principal plane, a plane inclined from a c-plane in an m-axis direction in a range from 60° to 90° both inclusive; an underlayer provided on the nitride semiconductor substrate and including a first layer and a second layer that are stacked on each other, the first layer including Alx2Inx1Ga(1-x1-x2)N (0<x1<1, 0?x2<1) and having a dislocation along an intersection line of the principal plane of the nitride semiconductor substrate and a (1-100) plane, the second layer including Aly2Iny1Ga(1-y1-y2)N (0<y1<1, 0?y2<1) and having a dislocation along an intersection line of the principal plane of the nitride semiconductor substrate and a (0001) plane; and a device layer including an active layer provided on the underlayer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 11, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yuusuke Nakayama
  • Patent number: 12002677
    Abstract: A processing device and a processing method for a solid structure are used to perform a processing procedure on the solid structure. The processing device for the solid structure of the invention provides energy to the solid structure by various electromagnetic radiation sources to cause the solid structure to generate qualitative changes or defects, that is, to form a modified layer. Stress and/or hardness of the modified layer are/is different from that of other non-processed areas.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: June 4, 2024
    Assignees: HIGHLIGHT TECH CORP., Finesse Technology Co., Ltd.
    Inventors: Chwung-Shan Kou, Wen-Yung Yeh
  • Patent number: 11996340
    Abstract: A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ying-Liang Chuang
  • Patent number: 11994440
    Abstract: Systems and methods are disclosed for packaging sensors for use in high temperature environments. In one example implementation, a sensor device includes a header; one or more feedthrough pins extending through the header; and a sensor chip disposed on a support portion of the header. The sensor chip includes one or more contact pads. The sensor device further includes one or more wire bonded interconnections in electrical communication with the respective one or more contact pads and the respective one or more feedthrough pins. The sensor device includes a first sealed enclosure formed by at least a portion of the header. The first sealed enclosure is configured for enclosing and protecting at last the one or more wire bonded interconnections and the one or more contact pads from an external environment.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 28, 2024
    Assignee: KULITE SEMICONDUCTOR PRODUCTS, INC.
    Inventors: Alexander A. Ned, Leo Geras, Sorin Stefanescu
  • Patent number: 11996395
    Abstract: A display device and a method of manufacturing the display device are proposed. The method may include disposing light emitting elements on a first transfer film; stretching the first transfer film so that the plurality of light emitting elements are spaced apart from each other; transferring the light emitting elements onto a thin film transistor array substrate; and removing the transfer film from the light emitting elements.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 28, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin Woo Choi, Min Woo Kim, Dae Ho Song, Hyung Il Jeon
  • Patent number: 11990427
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
  • Patent number: 11990484
    Abstract: The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 21, 2024
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Richard Price, Brian Cobb, Neil Davies
  • Patent number: 11990373
    Abstract: A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: May 21, 2024
    Assignee: SOCIONEXT INC.
    Inventor: Toyoji Sawada