Patents Examined by Vu A Vu
  • Patent number: 11990484
    Abstract: The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 21, 2024
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Richard Price, Brian Cobb, Neil Davies
  • Patent number: 11990373
    Abstract: A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: May 21, 2024
    Assignee: SOCIONEXT INC.
    Inventor: Toyoji Sawada
  • Patent number: 11990427
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
  • Patent number: 11990477
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 11984699
    Abstract: Provided is an optical semiconductor device including: a wavelength tunable laser element; a beam splitter that splits an outgoing beam of the wavelength tunable laser element into a first light beam and a second light beam parallel to each other, and outputs the first light beam and the second light beam; and an etalon that transmits the first light beam and the second light beam, wherein an optical path length to the first light beam of the etalon is different from an optical path length to the second light beam of the etalon.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 14, 2024
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Hiromitsu Kawamura
  • Patent number: 11978699
    Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: May 7, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sylvester Ankamah-Kusi, Yiqi Tang, Rajen Manicon Murugan, Sreenivasan K. Koduri
  • Patent number: 11978756
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 7, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Sonarith Chhun
  • Patent number: 11978695
    Abstract: A semiconductor package includes a first redistribution substrate, a connection substrate on the first redistribution substrate and having a first opening and a second opening that penetrate the connection substrate, a semiconductor chip on the first redistribution substrate and in the first opening of the connection substrate, a chip module on the first redistribution substrate and in the second opening of the connection substrate, and a molding layer that covers the semiconductor chip, the chip module, and the connection substrate. The chip module includes an inner substrate and a first passive device on the inner substrate. In the second opening, the molding layer covers the first passive device on the inner substrate.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: May 7, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Uk Kim
  • Patent number: 11973041
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
  • Patent number: 11973320
    Abstract: A Vertical Cavity Surface Emitting Laser (VCSEL) includes a VCSEL array, a multitude of detectors, a first electrical laser contact, and at least one second electrical laser contact. The VCSEL array comprises a multitude of laser diodes, each laser diode including an optical resonator having a first distributed Bragg reflector, a second distributed Bragg reflector and an active layer for light emission, the active layer being arranged between the first distributed Bragg reflector and the second distributed Bragg reflector. The first electrical laser contact and the at least one second electrical laser contact are arranged to provide an electrical drive current to electrically pump the optical resonators of the laser diodes. Each detector is arranged to generate an electrical self-mixing interference measurement signal associated to at least one laser diode upon reception of the laser light.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 30, 2024
    Inventor: Philipp Henning Gerlach
  • Patent number: 11967801
    Abstract: A structure having first and second layers is disposed on a substrate. The second layer is disposed on the first layer, is compressively strained, and comprises the alloy including germanium and tin. The structure comprises first and second members spaced a distance from each other along a direction, a strip located between the first and second members and extending along an axis intersecting the direction, and arms connecting the first and second members to a first end of the strip. The first and second members, the strip and the arms comprise respective portions of the first and second layers. A portion of the first layer at the strip and arms is removed such that the strip and arms become suspended and the arms remain anchored to the first layer via the first and second members. Tensile strain is induced in the alloy via the arms. The alloy may perform lasing.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: April 23, 2024
    Assignee: NanoPro AB
    Inventors: Ahmad Abedin, Mikael Östling
  • Patent number: 11955463
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 9, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Patent number: 11955767
    Abstract: In an embodiment a radiation-emitting component includes a first semiconductor chip configured to generate first primary electromagnetic radiation, a second semiconductor chip configured to generate second primary electromagnetic radiation, a first conversion element configured to partially convert the first and/or the second primary electromagnetic radiation into a first secondary radiation, wherein the first semiconductor chip is a first semiconductor laser diode, wherein the first primary electromagnetic radiation is blue primary radiation and wherein the first secondary radiation is green secondary radiation and a first optical element arranged between radiation emitting surfaces of the first semiconductor chip and the second semiconductor chip, wherein the first optical element is reflective for the first primary radiation and the second primary radiation.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 9, 2024
    Assignee: OSRAM OLED GmbH
    Inventors: Jörg Erich Sorg, David Racz
  • Patent number: 11948876
    Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ling-Wei Li, Jung-Hua Chang, Cheng-Lin Huang
  • Patent number: 11948911
    Abstract: The present disclosure provides a semiconductor packaging method and a semiconductor package device. The semiconductor packaging method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate, where a first end of the metal part is exposed by protruding over a surface of the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 2, 2024
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Guoqing Yu
  • Patent number: 11948928
    Abstract: A display apparatus, including a circuit substrate, a driving unit and a light-emitting unit is provided. The driving unit is disposed on the circuit substrate. The light-emitting unit is disposed on the circuit substrate. A thickness of the driving unit is substantially the same as a thickness of the light-emitting unit.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Au Optronics Corporation
    Inventors: Yang-En Wu, Shih-Hsiung Lin
  • Patent number: 11941485
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, François Lefloch, Fabrice Nemouchi, Maud Vinet
  • Patent number: 11942754
    Abstract: The present invention discloses a driving current correction method and apparatus for multiple laser devices, and a laser projector.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 26, 2024
    Assignee: GOER OPTICAL TECHNOLOGY CO., LTD.
    Inventors: Lebao Yang, Xianbin Wang
  • Patent number: 11942352
    Abstract: A manufacturing method of an LED display is disclosed. The method includes picking up a plurality of LED chips spaced apart at a first interval with a stretchable stamp, spacing apart the plurality of LED chips at a second interval by stretching the stretchable stamp, and transferring the plurality of LED chips to a target substrate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 26, 2024
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Dahl Young Khang, Byong Joo Lee
  • Patent number: 11942762
    Abstract: A surface-emitting laser device according to an embodiment comprises: a first electrode; a substrate arranged on the first electrode; a first reflection layer arranged on the substrate; an active region arranged on the first reflection layer and including a cavity; an opening region arranged on the active region and including an aperture and an insulation region; a second reflection layer arranged on the opening region; a second electrode arranged on the second reflection layer; and a delta doping layer arranged in the opening region. The thickness of the insulation region becomes thinner in the direction of the aperture, and the delta doping layer can be arranged at the aperture.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: March 26, 2024
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Jeong Sik Lee, Sang Heon Han, Keun Uk Park, Yeo Jae Yoon