Abstract: A semiconductor device includes a first die. The first die includes a first dielectric bonding layer thereon and a plurality of first dielectric bonding patterns in the first dielectric bonding layer. A composition of the first dielectric bonding patterns is different from a composition of the first dielectric bonding layer.

Abstract: A method for producing a light emitting diode supply substrate for transferring a plurality of light emitting diodes to a supply destination, including: a first mounting step of mounting a plurality of light emitting diodes on a supply substrate; a selective removal step of selectively removing defective light emitting diodes on the supply substrate, and a second mounting step of transferring a normal light emitting diode to a position where the defective light emitting diode has been arranged on the supply substrate. Thus, a method produces a light emitting diode supply substrate capable of producing a light emitting diode supply substrate capable of transferring a plurality of normal light emitting diodes to a supply destination.

Abstract: A method of manufacturing a semiconductor device in a semiconductor body is proposed. The method includes processing a semiconductor body at a first surface of the semiconductor body. The method further includes attaching the semiconductor body to a carrier via the first surface. The carrier includes an inner part and an outer part at least partly surrounding the inner part. The method further includes processing the semiconductor body at a second surface opposite to the first surface. The method further includes detaching the inner part of the carrier from the semiconductor body.

Abstract: A manufacturing method of a structure intended for assembly with another structure by self-aligning bonding by hydrophilic contrast, including the following successive steps: a) definition of pads on the side of the first face of a first substrate; b) transfer of a second substrate on the side of the first face of the first substrate; c) formation on the sides and/or on a peripheral part of the upper face of the pads, of a material more hydrophobic than a material of the upper face of the pads; and d) removal of the second substrate.

Abstract: A display device is provided. The display device includes a display region which includes a first display region and a second display region, where the first display region includes a plurality of first pixels, and the second display region includes a plurality of second pixels and at least one light transmission region, where the light transmission region has light transmittance that is higher than light transmittance of the first pixel and light transmittance of the second pixel, and the second display region has light transmittance that is higher than light transmittance of the first display region.

Abstract: A semiconductor structure includes fins protruding from a substrate and separated by a dielectric layer, each semiconductor fin including a plurality of semiconductor layers, source/drain (S/D) features disposed in the semiconductor fins, a first metal gate stack and a second metal gate stack disposed over the semiconductor fins and adjacent to the S/D features, where the first and the second metal gate stacks each include a top portion and a bottom portion disposed below the top portion, and where the bottom portion is interleaved with the semiconductor layers, and an isolation feature disposed on the dielectric layer and in contact with a sidewall surface of each of the first and the second metal gate stacks, where the isolation feature protrudes from the top portion of the first and the second metal gate stack, and where the isolation feature includes two compositionally different dielectric layers.

Abstract: A first carrier has a first plate. A tape is disposed on the first plate. A second plate is disposed over the first plate. The second plate has a trench aligned to the tape and an opening formed through the second plate over the tape. A singulated semiconductor package is disposed on the tape in the opening of the second plate. A second carrier has a static datum and a movable datum. The movable datum is moved toward the static datum. An aperture substrate is disposed around the static datum and movable datum. A manufacturing process is performed on the aperture substrate.

Abstract: A stacked FET architecture includes isolated pockets for replacement metal gates for top and bottom nanosheet field-effect transistors. Different work function metals are employed for the metal gates of n-type and p-type FETs. The architecture allows flexibility in providing electrically connected or unconnected metal gates.

Abstract: A method for making semiconductor devices includes: attaching a substrate with a plurality of electronic components onto a composite tape having an adhesive layer which is sensitive to ultraviolet (UV) irradiation and a UV-transparent base film, wherein the substrate is attached onto the adhesive layer of the composite tape; placing the substrate and the composite tape on a UV-transparent carrier, wherein the UV-transparent carrier is in contact with the UV-transparent base film of the composite tape; singulating the substrate into a plurality of semiconductor devices each having one of the plurality of electronic components; depositing a shielding material on the plurality of semiconductor devices to form a shielding layer on each of the plurality of semiconductor devices; irradiating a UV light to the composite tape through the UV-transparent carrier to reduce adhesivity of the adhesive layer; and detaching the plurality of semiconductor devices from the UV-transparent carrier.

Abstract: According to one embodiment, a semiconductor device includes a bed portion, a semiconductor element, and a connector. The semiconductor element has a first electrode electrically connected to the bed portion and a second electrode facing away from the bed portion. The connector includes a first connection portion with a first surface electrically connected to the second electrode. The first surface is inclined in a direction from an outer edge portion of the first surface toward a center of the first surface. A lead portion of the connector is electrically connected to the first connection portion and spaced away from the bed portion.

Abstract: A die bonding method is disclosed, through coating bonding adhesive on front side of device wafer and bonding carrier wafer thereto, back-side connection structure can be formed on back side of device wafer to lead out an interconnect structure in device wafer to back side of device wafer, and dies thereon can be bonded at front sides to target wafer. Moreover, after device wafer is debonded from carrier wafer, the bonding adhesive is retained on front side of device wafer to provide protection to front side of device wafer during subsequent dicing of device wafer, and to avoid particles or etching by-products produced during dicing process from adhering to front side of device wafer. Such etching by-products are subsequently removed along with the bonding adhesive, ensuring cleanness of front sides of individual dies resulting from dicing process and improved quality of bonding of dies at front sides to target wafer.

Abstract: A temporary substrate, which is detachable at a detachment temperature higher than 1000° C. comprises: a semiconductor working layer extending along a main plane, a carrier substrate, an intermediate layer having a thickness less than 20 nm arranged between the working layer and the carrier substrate, a bonding interface located in or adjacent the intermediate layer, gaseous atomic species distributed according to a concentration profile along the axis normal to the main plane, the atoms remaining trapped in the intermediate layer and/or in an adjacent layer of the carrier substrate with a thickness less than or equal to 10 nm and/or in an adjacent sublayer of the working layer with a thickness less than or equal to 10 nm when the temporary substrate is subjected to a temperature lower than the detachment temperature.

Abstract: A semiconductor device includes an active region, including: a semiconductor layer, having a first surface, including a collector layer, a base layer and an emitter layer sequentially stacked, and the first surface being a surface of the emitter layer facing away from the base layer; an emitter mesa and an emitter electrode sequentially disposed on the emitter layer; a first dielectric layer, covering a top surface of the emitter electrode, extending along a side surface of the emitter electrode to cover part of the first surface exposed outside the emitter electrode, and defining a first opening; a second dielectric layer, covering the first dielectric layer, and defining a second opening connected to the first opening; and a base electrode, connected to the base layer through the first opening and the second opening, and extending to cover at least part of the second dielectric layer adjacent to the second opening.

Abstract: A base plate configured to be attached to a semiconductor substrate, wherein the base plate is configured to remain attached to the semiconductor substrate during a sequence of processing steps performed on the semiconductor substrate, and the base plate is made from a material having a Young's modulus larger than 300 GPa.

Abstract: A packaging method includes: obtaining a carrier and processing a first pad on a side surface of the carrier; processing a second pad on a side surface of the first pad away from the carrier; obtaining a first sealing material, pressing the first sealing material with the second pad, the first pad, and a side surface of the carrier on which the first pad is arranged to form a first sealing member; processing a chip pad on a side surface of each first pad away from the second pad; mounting a chip on at least one chip pad; obtaining a second sealing material, pressing the second sealing material with the chip, a side surface of the chip pad away from the second pad, and a side surface of the first sealing member near the first pad, to form a second sealing member.

Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.

Abstract: The present disclosure relates to a semiconductor chip that allows electrical connections to be protected and a manufacturing method therefor. A semiconductor chip has a strip-shaped region including a plurality of recesses on a side surface thereof. The recesses are arranged in a matrix of rows and columns on the side surface of the semiconductor chip or in a zig-zag pattern in the region. At least two of the strip-shaped regions are formed. The strip-shaped regions are formed in different positions between the vicinity of the center and opposed ends of the side surface. The strip-shaped region is partly inclined. The present disclosure can be applied for example to a semiconductor chip for a semiconductor device in which connections for electrically connecting the semiconductor chip and the substrate are protected with underfill.

Abstract: The manufacturing method of a semiconductor device includes providing a word line structure and a hard mask stack on the word line structure. The word line structure includes an active area, a word line, an isolation structure and a protection layer, the word line covers a portion of the active area, the isolation structure is adjacent to the active area and the word line, and the protection layer covers the active area, the word line, and the isolation structure. A first photolithography process is performed to etch the hard mask stack by using a photomask along a first direction. A second photolithography process is performed to etch the hard mask stack by using a photomask along a second direction. A protection pillar covering the portion of the active area by etching the protection layer is formed by using the hard mask stack as a mask.

Abstract: A lift-off method includes joining a transfer substrate to a face side of an optical device layer of an optical device wafer with a joining member interposed therebetween, thereby making up a composite substrate, applying a pulsed laser beam having a wavelength transmittable through the epitaxy substrate and absorbable by a buffer layer, from a reverse side of the epitaxy substrate of the optical device wafer, thereby breaking the buffer layer, and an optical device layer transferring step of peeling off the epitaxy substrate from the optical device layer and transferring the optical device layer to the transfer substrate. The optical device layer transferring step includes the step of applying a bending moment to an area of the composite substrate that includes an outer peripheral portion thereof while holding an area of the composite substrate that includes a central portion thereof.

Abstract: A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded to the light emitting structure via a metal-metal bond, such as a copper-copper bond, or with an inter-metallic compound bond.