Patents Examined by Vu A Vu
  • Patent number: 10930849
    Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins
  • Patent number: 10916555
    Abstract: A structure of memory cell includes a memory gate structure, disposed on a substrate, wherein the substrate has an indent region aside the memory gate structure. A selection gate structure is disposed on the substrate at the indent region aside the memory gate structure. A first insulation layer is at least disposed between the memory gate structure and selection gate structure.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chin-Chin Tsai
  • Patent number: 10910354
    Abstract: A semiconductor device die transfer apparatus includes a first frame to hold a wafer tape having a plurality of semiconductor device die disposed on a side of the wafer tape and a second frame to secure a product substrate having a circuit trace thereon. The second frame is configured to secure the product substrate such that the circuit trace is disposed facing the plurality of semiconductor device die on the wafer tape. Additionally, a rotary transfer collet is disposed between the wafer tape and the product substrate. The rotary transfer collet has a rotational axis allowing rotation from a first position facing the wafer tape to pick a die of the plurality of semiconductor device die to a second position facing the circuit trace on the product substrate to release the die, thereby applying the die directly on the product substrate during a transfer operation.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: February 2, 2021
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Clinton Adams, Sean Kupcow, Andrew Huska
  • Patent number: 10910270
    Abstract: A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: February 2, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Jin Won Jeong, Byeung Soo Song, Dong Ki Shim, Jin Han Bae
  • Patent number: 10910286
    Abstract: Wafer-level system-in-package packaging method and package structure are provided. The method includes: forming a bonding structure, where the bonding structure includes a device wafer and a plurality of chips bonded to the device wafer, where the plurality of chips contains one or more first chips to-be-shielded; forming an encapsulation layer covering the plurality of chips; forming a trench in the encapsulation layer to surround each first chip of the one or more first chips; and forming a conductive material in the trench and on the encapsulation layer, where the conductive material includes a shielding housing, the shielding housing including a conductive sidewall formed in the trench and a conductive layer formed on a portion of the encapsulation layer above the each first chip and connected with the conductive sidewall.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 2, 2021
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10903345
    Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: January 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yufei Xiong, Yunlong Liu, Hong Yang, Ho Lin, Tianping Lv, Sheng Zou, Qiuling Jia
  • Patent number: 10896817
    Abstract: A laser irradiation apparatus includes a light source that generates a laser beam, a projection lens that radiates the laser beam onto a predetermined region of an amorphous silicon thin film deposited on each of a plurality of thin film transistors on a glass substrate, and a projection mask pattern provided on the projection lens and has a plurality of openings so that the laser beam is radiated onto each of the plurality of thin film transistors, wherein the projection lens radiates the laser beam onto the plurality of thin film transistors on the glass substrate, which moves in a predetermined direction, through the projection mask pattern, and the projection mask pattern is provided such that the openings are not continuous in one column orthogonal to the moving direction.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 19, 2021
    Assignees: V Technology Co. Ltd., Sakai Display Products Corporation
    Inventors: Michinobu Mizumura, Nobutake Nodera, Yoshiaki Matsushima, Masakazu Tanaka, Takao Matsumoto
  • Patent number: 10896840
    Abstract: Implementations of a method of increasing the adhesion of a tape. Implementations may include: mounting a tape to a frame, mounting a substrate to the tape, heating the tape after mounting the substrate at one or more temperatures for a predetermined period of time, and increasing an adhesion of the tape to the substrate through heating the tape.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 19, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10892308
    Abstract: A method of fabricating a display panel may include forming an oxide semiconductor pattern on a base layer including a first region and a second region, etching first, second, and third insulating layers to form a first groove that overlaps the second region, forming electrodes on the third insulating layer, forming a fourth insulating layer on the third insulating layer to cover the electrodes, thermally treating the fourth insulating layer, forming an organic layer to cover the fourth insulating layer, and forming an organic light emitting diode on the organic layer.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 12, 2021
    Inventors: Kyoungseok Son, Myounghwa Kim, Eoksu Kim, Taesang Kim, Masataka Kano
  • Patent number: 10892277
    Abstract: Embodiments of 3D memory devices having one or more high-? dielectric layers and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a high-? dielectric layer above the substrate and a plurality of interleaved conductor and dielectric layers above the high-? dielectric layer, and a semiconductor plug disposed above the substrate and in an opening of the high-? dielectric layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 10892349
    Abstract: Electronic apparatus, systems, and methods in a variety of applications can include a fin field effect transistor (FinFET) having a deposited fin body. Such a FinFET can be implemented as an access transistor in a circuit of an integrated circuit. In an embodiment, an array of FinFETs having a deposited fin bodies can be disposed on digitlines. For the array of FinFETs having a deposited fin bodies structured in memory cells of a memory, the digitlines can be coupled to sense amplifiers. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10886703
    Abstract: A distributed Bragg reflector (DBR) structure on a substrate includes a high refractive index layer comprising titanium oxide (TiO2) and a low refractive index layer having a high carbon region and at least one low carbon region that contacts the high refractive index layer. Multiple layers of the high refractive index layer and the low refractive index layer are stacked. Typically, the multiple layers of the high refractive index layer and the low refractive index layer are stacked to a thickness of less than 10 microns. Each of the respective layers of the high refractive index layer and the low refractive index layer have a thickness of less than 0.2 microns.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: January 5, 2021
    Assignee: Lumileds LLC
    Inventors: Ken Shimizu, Hisashi Masui, Ted Wangensteen
  • Patent number: 10886315
    Abstract: The present disclosure provides a photosensitive assembly and formation method thereof, a lens module, and an electronic device. The method for forming the photosensitive assembly includes providing a transparent cover plate; providing a photosensitive chip, including a photosensitive region and a peripheral region surrounding the photosensitive region; bonding the transparent cover plate to the photosensitive chip through a bonding layer, the bonding layer located in the peripheral region of the photosensitive chip, and the transparent cover plate, the bonding layer, and the photosensitive chip enclosing a cavity that accommodates the photosensitive region; and forming a sealing layer to at least cover the sidewall of the bonding layer and the sidewall of the transparent cover plate. According to the present disclosure, a sealing layer is formed on the sidewall of the bonding layer and the sidewall of the transparent cover plate to increase the effect for sealing the cavity.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: January 5, 2021
    Assignee: Ningbo Semiconductor International Corporation
    Inventor: Da Chen
  • Patent number: 10886491
    Abstract: Process for preparing a metal containing layer, the process comprising (i) at least one step of co-vaporization, at a pressure which is lower than 10?2 Pa, of a) at least one first metal selected from Li, Na, K, Rb and Cs and b) at least one second metal selected Mg, Zn, Hg, Cd and Te from a metal alloy provided in a first vaporization source which is heated to a temperature between 100° C. and 600° C., and (ii) at least one subsequent step of deposition of the first metal on a surface having a temperature which is below the temperature of the first vaporization source, wherein in step (i), the alloy is provided at least partly in form of a homogeneous phase comprising the first metal and the second metal, electronic devices comprising such materials and process for preparing the same.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: January 5, 2021
    Assignee: Novaled GmbH
    Inventors: Tomas Kalisz, Francois Cardinali, Jerome Ganier, Uwe Gölfert, Vygintas Jankus, Carsten Rothe, Benjamin Schulze, Steffen Willmann
  • Patent number: 10879131
    Abstract: The present disclosure provides a method for method for forming a semiconductor structure, including providing a substrate with a first well region of a first conductivity type, forming a silicon layer over the first well region, forming a first silicon fin over the first well region, and applying a silicon-free gas source upon the first silicon fin.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsungyu Hung, Pei-Wei Lee, Pang-Yen Tsai
  • Patent number: 10879263
    Abstract: Embodiments of a three-dimensional (3D) memory device are disclosed. The 3D memory device has an architecture with an increased number of bit lines. In an example, the 3D memory device includes a substrate, a plurality of memory strings each extending vertically above the substrate in a memory region, and a plurality of bit lines over the plurality of memory strings. At least one of the plurality of bit lines is electrically connected to a single one of the plurality of memory strings.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: December 29, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Lei Xue
  • Patent number: 10879674
    Abstract: An optical device includes a gallium and nitrogen containing substrate comprising a surface region configured in a (20-2-1) orientation, a (30-3-1) orientation, or a (30-31) orientation, within +/?10 degrees toward c-plane and/or a-plane from the orientation. Optical devices having quantum well regions overly the surface region are also disclosed.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, You-Da Lin, Christiane Elsass
  • Patent number: 10872822
    Abstract: In a method of manufacturing a circuit including a MOSFET disposed in a MOSFET region and a negative capacitance FET (NCFET) disposed in a NCFET region, a dielectric layer is formed over a channel layer in the MOSFET region and the NCFET region. A first metallic layer is formed over the dielectric layer in the MOSFET region and the NCFET region. After the first metallic layer is formed, an annealing operation is performed only in the NCFET region. After the annealing operation, the first metallic layer is removed from the MOSFET region and the NCFET region. The annealing operation includes irradiating the first metallic layer and the dielectric layer in the NCFET region with an energy beam.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ling-Yen Yeh, Carlos H. Diaz, Wilman Tsai
  • Patent number: 10872833
    Abstract: The invention relates to an electronic module (6), in particular a power module, having at least one electrical/electronic component (7) and having a housing (8), which at least partly extends around the component (7), wherein the housing (8) is made of cement composite (1), and wherein the cement composite (1) has at least one particulate filler (2). According to the invention, the particulate filler (2) has aluminum nitride particles (3), which each have a coating only of aluminum oxide (4).
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 22, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Bernd Rometsch, Georg Hejtmann, Martin Rittner, Stefan Kaessner
  • Patent number: 10867899
    Abstract: A method of manufacturing a semiconductor package includes: (1) providing a first passivation layer on a carrier; (2) patterning the first passivation layer to define a first hole; (3) disposing a first seed layer on the first hole; (4) disposing a first conductive layer on the first seed layer; (5) replacing the carrier with a second passivation layer; (6) patterning the second passivation layer to define a second hole exposing the first seed layer; and (7) disposing a second conductive layer on the exposed first seed layer through the second hole.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: December 15, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Fu Sung, Shin-Hua Chao, Ming-Chi Liu, Hung-Sheng Chen