Patents Examined by Vu A Vu
  • Patent number: 12218141
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 12205953
    Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.
    Type: Grant
    Filed: December 14, 2023
    Date of Patent: January 21, 2025
    Assignee: SOCIONEXT INC.
    Inventors: Toshio Hino, Junji Iwahori
  • Patent number: 12205866
    Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chia Chiu, Li-Han Hsu
  • Patent number: 12205971
    Abstract: The re is provided a fingerprint identification module, including a substrate having a fingerprint identification area and a peripheral area; a photoelectric sensing structure in the fingerprint identification area, and including pixel units; each pixel unit includes a thin film transistor having a gate electrode coupled to a corresponding gate line and a first electrode coupled to a corresponding signal sensing line; the fingerprint identification area includes a photosensitive region, the pixel unit in the photosensitive region further includes a photoelectric sensor including a third electrode, a photosensitive pattern and a fourth electrode which are sequentially stacked along a direction away from the substrate, and the third electrode is coupled to a second electrode of the thin film transistor in the same pixel unit as that where the photoelectric sensor is located; an area ratio of the photoelectric sensor to the pixel unit corresponding thereto ranges from 40% to 90%.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 21, 2025
    Assignees: Beijing BOE Sensor Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kuiyuan Wang, Cheng Li, Yue Geng, Chaoyang Qi, Yi Dai, Zefei Li, Xiaoguan Li, Yajie Feng, Yingzi Wang
  • Patent number: 12193290
    Abstract: Provided are a display substrate, a preparation method thereof, and a display device. The display substrate includes a display region and a bonding region on one side of the display region. The bonding region at least includes a lead area; the display region includes a plurality of data lines and a plurality of data fanout lines, the lead area includes a plurality of lead wires, and orthographic projections of the plurality of data lines and the plurality of data fanout lines on a plane of the display substrate are at least partially overlapped. At least one lead wire is connected to the data line through the data fanout line. In the lead area, an orthographic projection of any one of the lead wires on the plane of the display substrate and orthographic projections of other lead wires on the plane of the display substrate have no overlap region.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: January 7, 2025
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yuanjie Xu, Benlian Wang, Lili Du, Zhenhua Zhang, Yuxin Zhang, Pan Xu
  • Patent number: 12191285
    Abstract: An optical projection device and a method of producing the optical projection device are described. The optical projection device includes: a plurality of LEDs (light-emitting diodes), the LEDs each including a semiconductor mesa laterally spaced apart from one another by a grid structure. Each of the semiconductor mesas includes an n-type material and a p-type material adjoining at least partly the n-type material. The grid structure at least partly laterally surrounds at least the n-type material of each of the semiconductor mesas. The grid structure includes a conductive material that electrically interconnects the n-type material of the semiconductor mesas. The grid structure is configured to block optical crosstalk between light emitted by the LEDs.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 7, 2025
    Assignee: Infineon Technologies AG
    Inventors: Dietrich Bonart, Frank Singer
  • Patent number: 12185603
    Abstract: A display panel, a manufacturing method thereof, and a display device are provided. In the display panel, a first undercut structure and a second undercut structure are formed along a vertical direction of an overlappingly connecting hole of the first electrode layer and the auxiliary electrode layer. Therefore, an overlappingly connecting area between the first electrode layer and the auxiliary electrode layer can be enlarged. As such, the first electrode layer can be ensured to have high transparency and good conductivity, thereby solving an issue of IP drop of the first electrode. In addition, by using this undercut structure as well as using a metal line layer to overlappingly connect the first electrode layer with the auxiliary electrode layer, the overlappingly connecting area between the first electrode layer and the auxiliary electrode layer can be enlarged without reducing an aperture ratio of the display panel.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: December 31, 2024
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Weijing Zeng
  • Patent number: 12185588
    Abstract: A display device according to an embodiment includes: a substrate including a display area, a dummy area, and a peripheral area; a passivation layer positioned in the display area, the dummy region, and the peripheral area of the substrate; a first adhesive auxiliary layer positioned on the passivation layer and positioned in the dummy region; a dummy pixel defining layer positioned on the first adhesive auxiliary layer and including a hydrophobic material; a second adhesive auxiliary layer positioned on the passivation layer, positioned in the peripheral area, and including a lateral side contacting the dummy pixel defining layer; a common voltage transmitter positioned in the peripheral area; and a common electrode connected to the common voltage transmitter, and positioned on the second adhesive auxiliary layer and the dummy pixel defining layer.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: December 31, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Yoon Kim, Yool Guk Kim
  • Patent number: 12183636
    Abstract: A semiconductor substrate includes: a base substrate; a removal layer, and of which at least a portion is to be removed by performing etching; a semiconductor epitaxial layer provided above the removal layer; and a support member for supporting the semiconductor epitaxial layer in a state where the support member is in contact with side surfaces of the base substrate, the removal layer, and the semiconductor epitaxial layer such that the semiconductor epitaxial layer is positioned above the base substrate, the support member being cut off in a region in contact with the removal layer due to application of a force to the semiconductor epitaxial layer. The thickness of at least a portion of a region of the support member in contact with the removal layer is smaller than the thickness of other regions that are different from the at least the portion of the region in the support member.
    Type: Grant
    Filed: December 11, 2023
    Date of Patent: December 31, 2024
    Assignee: Filnex Inc.
    Inventor: Mitsuhiko Ogihara
  • Patent number: 12183753
    Abstract: An image sensor includes a first photodiode and a second photodiode. The image sensor further includes a first color filter over the first photodiode; and a second color filter over the second photodiode. The image sensor further includes a first microlens over the first color filter and a second microlens over the second color filter. The image sensor further includes a first electro-optical (EO) film between the first color filter and the first microlens, wherein a material of the first EO film is configured to change refractive index in response to application of an electrical field. The image sensor further includes a second EO film between the second color filter and the second microlens, wherein a material of the second EO film is configured to change refractive index in response to application of an electrical field.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Lin Chen, Ching-Chung Su, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 12176283
    Abstract: A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: December 24, 2024
    Assignee: Infineon Technologies AG
    Inventor: Petteri Palm
  • Patent number: 12176373
    Abstract: Disclosed is a light receiving element including an on-chip lens, a wiring layer, and a semiconductor layer disposed between the on-chip lens and the wiring layer. The semiconductor layer includes a photodiode, a first transfer transistor that transfers electric charge generated in the photodiode to a first charge storage portion, a second transfer transistor that transfers electric charge generated in the photodiode to a second charge storage portion, and an interpixel separation portion that separates the semiconductor layers of adjacent pixels from each other, for at least part of the semiconductor layer in the depth direction. The wiring layer has at least one layer including a light blocking member. The light blocking member is disposed to overlap with the photodiode in a plan view.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: December 24, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yoshiki Ebiko, Koji Neya, Takuya Sano
  • Patent number: 12176306
    Abstract: An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 24, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Heung Lee, Soo Cheol Kang, Seong Il Kim, Hae Cheon Kim, Youn Sub Noh, Ho Kyun Ahn, Jong Won Lim, Sung Jae Chang, Hyun Wook Jung
  • Patent number: 12176301
    Abstract: A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring. The package structure also includes a substrate on a second surface of the redistribution structure through third bonding elements and in electrical connection with the semiconductor die.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chen Lai, Chin-Hua Wang, Ming-Chih Yew, Li-Ling Liao, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 12176672
    Abstract: An optical device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, a light sensitive component (e.g., a photodetector) in the dielectric layer and coupled to the waveguide, and a plurality of light isolation structures in at least one of the substrate or the dielectric layer and configured to prevent stray light from reaching the light sensitive component. In some embodiments, a light isolation structure in the plurality of light isolation structures includes two opposing sidewalls and a filling material between the two opposing sidewalls. The two opposing sidewalls include an optical isolation layer. The filling material is characterized by a coefficient of thermal expansion (CTE) matching a CTE of at least one of the substrate or the dielectric layer.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: December 24, 2024
    Assignee: Psiquantum, Corp.
    Inventors: Eric Dudley, Yong Liang, Faraz Najafi, Vimal Kamineni, Ann Melnichuk
  • Patent number: 12176335
    Abstract: A semiconductor device has a first semiconductor package including a substrate and an encapsulant deposited over the substrate. An adhesive tape is disposed on the encapsulant. A conductive via is formed by trench cutting through the adhesive tape and encapsulant to expose the substrate. A second semiconductor package is disposed over the adhesive tape opposite the first semiconductor package. The first semiconductor package and second semiconductor package are bonded together by the adhesive tape.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: December 24, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: GunHyuck Lee, SangHyun Son, Yujeong Jang, Hyeoneui Lee
  • Patent number: 12176261
    Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12176239
    Abstract: A method includes transferring multiple discrete components from a first substrate to a second substrate, including illuminating multiple regions on a top surface of a dynamic release layer, the dynamic release layer adhering the multiple discrete components to the first substrate, each of the irradiated regions being aligned with a corresponding one of the discrete components. The illuminating induces a plastic deformation in each of the irradiated regions of the dynamic release layer. The plastic deformation causes at least some of the discrete components to be concurrently released from the first substrate.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: December 24, 2024
    Assignee: KULICKE & SOFFA NETHERLANDS B.V.
    Inventors: Val Marinov, Ronn Kliger, Matthew R. Semler
  • Patent number: 12176334
    Abstract: A display panel includes a backplate, a eutectic bonding layer and an auxiliary layer that are located at a side of the backplate, and a plurality of light-emitting element bodies. The auxiliary layer includes a plurality of first members and a second member. At least one first member of the plurality of first members surrounds one part of the eutectic bonding layer, and the second member surrounds the plurality of first members. Each of the plurality of light-emitting element bodies is located at a side of the eutectic bonding layer and is connected to one part of the eutectic bonding layer.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: December 24, 2024
    Assignee: Shanghai Tianma Micro-Electronics Co., Ltd.
    Inventor: Canyuan Zhang
  • Patent number: 12170226
    Abstract: A method for separating dies from a semiconductor substrate having dies adjoining a first surface of the substrate includes: attaching the substrate to a carrier via the first surface; generating first modifications by introducing laser irradiation into an interior of the substrate via a second surface of the substrate, the first modifications extending between the first surface and a vertical level in the interior that is being spaced from the second surface, the first modifications laterally surrounding the dies; generating second modifications by introducing laser irradiation into the interior via the second surface, the second modifications sub-dividing the substrate into a first part between the first surface and the second modifications, and a second part between the second surface and the second modifications; separating the parts along a first separation area defined by the second modifications; and separating the dies along a second separation area defined by the first modifications.
    Type: Grant
    Filed: March 28, 2024
    Date of Patent: December 17, 2024
    Assignee: Infineon Technologies AG
    Inventors: Franz-Josef Pichler, Benjamin Bernard, Mario Stefenelli