Patents Examined by W. C. Tupman
  • Patent number: 4283734
    Abstract: A batch production process for millimeter wave sources of a module type. This module type consists of a basic metallic support, bearing a diode under the form of a semiconductor chip soldered on a projection of the support, the diode being surrounded by a dielectric substance forming a medium extending up to half a wavelength on the same support, with a metallization covering the surrounding medium and connected with the top of the chip by a metallic block. In a first embodiment, the batch process is limited to the central part of the module i.e. the semiconductor chip, the block and only a part of the dielectric medium, as well as a part of the metallic support. In a second embodiment of the process, the collective production of the entire module is achieved.
    Type: Grant
    Filed: March 15, 1979
    Date of Patent: August 11, 1981
    Assignee: Thomson-CSF
    Inventor: Jacques Espaignol
  • Patent number: 4270262
    Abstract: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings.
    Type: Grant
    Filed: February 23, 1978
    Date of Patent: June 2, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Hori, Masaharu Kubo, Norikazu Hashimoto, Shigeru Nishimatsu, Kiyoo Itoh
  • Patent number: 4268950
    Abstract: An MOS read only memory, or ROM, is formed by a process compatible with standard silicon gate manufacturing methods. The ROM is programmed either after the top level of device interconnects has been patterned and sintered, usually the last step in the slice processing method before electrical testing of the devices, or after the electrical testing of the devices. All potential MOS transistors in the ROM array are initially at a logic "0" or a logic "1". Selected transistors are programmed by implanting ions of the appropriate impurity type through their gates and gate oxides into the silicon, using photoresist as an implant mask. Impurities are electrically activated by laser annealing, and residual oxide charge is removed by rf plasma anneal.
    Type: Grant
    Filed: June 5, 1978
    Date of Patent: May 26, 1981
    Assignee: Texas Instruments Incorporated
    Inventors: Pallab K. Chatterjee, Al F. Tasch, Jr.
  • Patent number: 4268951
    Abstract: Semiconductor devices with gate dimensions as small as 0.25 microns square have been fabricated using electron beam lithography and dry processing techniques. In particular, silicon gate, N-channel, metal-oxide-semiconductor (NMOS) field-effect-transistors (FET) have been produced. The devices and the process are especially adapted to bulk silicon based transistors.
    Type: Grant
    Filed: November 13, 1978
    Date of Patent: May 26, 1981
    Assignee: Rockwell International Corporation
    Inventors: Michael T. Elliott, Michael R. Splinter, Addison B. Jones, John P. Reekstin
  • Patent number: 4263709
    Abstract: A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.
    Type: Grant
    Filed: December 22, 1978
    Date of Patent: April 28, 1981
    Assignee: RCA Corporation
    Inventors: Charles E. Weitzel, Joseph H. Scott
  • Patent number: 4261096
    Abstract: A metallic ground grid is fabricated by forming a conductor on the isolation barrier of an integrated circuit through openings in a first insulated layer to a depth less than the first insulated layer, forming a second insulated layer on said first conductor to the height of the first insulated layer, and interconnecting selected areas of the integrated circuit and the first conductor through openings in the insulated layers by a second conductor.
    Type: Grant
    Filed: March 30, 1979
    Date of Patent: April 14, 1981
    Assignee: Harris Corporation
    Inventors: Thomas J. Sanders, William R. Morcom, Jacob A. Davis
  • Patent number: 4259779
    Abstract: The radiation resistance of an MOS transistor is improved by making the transistor in a manner such that, after the gate insulation layer is formed, all further steps are carried out at a relatively low temperature, i.e., less than about 900.degree. C. The source and drain regions are preferably formed by ion implantation with very little or no post implant thermal activation, and the metallization is applied by low temperature techniques.
    Type: Grant
    Filed: August 24, 1977
    Date of Patent: April 7, 1981
    Assignee: RCA Corporation
    Inventors: Alfred C. Ipri, Doris W. Flatley
  • Patent number: 4258465
    Abstract: An offset gate MIS device is fabricated by forming an insulating film with a gate insulator portion as a part thereof on the surface of a semiconductor substrate having one conductivity type, providing a gate electrode on a portion of the insulating film, using the gate electrode as a mask to apply impurities of the other conductivity type with a first impurity concentration to the surface of the semiconductor substrate through the insulating film, forming a shielding film on the surface of that portion of the insulating film which is near the gate insulator portion beneath the gate electrode, using the shielding film as a mask to remove an unmasked portion of the insulating film so as to selectively expose the surface of the semiconductor substrate, applying impurities of the other conductivity type with a second impurity concentration higher than the first impurity concentration to the exposed surface of the semiconductor substrate, and heating the resultant structure to diffuse the impurities into the semi
    Type: Grant
    Filed: May 26, 1978
    Date of Patent: March 31, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Tokumasa Yasui, Minoru Fukuda, Tatsumi Shirasu
  • Patent number: 4258466
    Abstract: An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not needed. These factors provide a very small cell size. The source and drain regions are formed prior to applying the first level polysilicon then covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas.
    Type: Grant
    Filed: November 2, 1978
    Date of Patent: March 31, 1981
    Assignee: Texas Instruments Incorporated
    Inventors: Chang-Kiang Kuo, Shyh-Chang Tsaur
  • Patent number: 4254546
    Abstract: In a photovoltaic cell which comprises: a substrate, a bottom electrode, a first layer of cadmium sulfide, a second layer of cuprous sulfide forming a barrier junction with said first layer and a top electrode, the improvement wherein said substrate is an insulative ceramic material and the bottom electrode is a conductive ceramic layer fused to said substrate. Said conductive layer is optionally coated with a metal having a high electrical conductivity.
    Type: Grant
    Filed: September 11, 1978
    Date of Patent: March 10, 1981
    Assignee: SES, Incorporated
    Inventor: Lee R. Ullery, Jr.
  • Patent number: 4253230
    Abstract: A planar, silicon barrier, Josephson junction and method of forming the jtion which does not require expensive high-resolution, lithography techniques such as electron beam or x-ray. The method includes an etching mask-etch process which forms the basic structure configuration using a (110)-cut silicon wafer. Subsequent to the etching process the mask is removed and a superconducting film is deposited on the previously formed silicon surface to produce a single crystal silicon barrier with good electrical properties.
    Type: Grant
    Filed: February 9, 1979
    Date of Patent: March 3, 1981
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Kenneth L. Davis
  • Patent number: 4253229
    Abstract: A method of making a narrow gate MESFET including the steps of placing a layered mask of nitride and polysilicon over a channel region for self-aligning in a substrate, oxidizing and then removing the polysilicon to reduce the remaining polysilicon width, etching the nitride to the polysilicon width, oxidizing the substrate where the nitride defines the gate therein, removing the nitride, and depositing metal on the gate to form the MESFET Schottky gate. Advantages of the improved MESFET include a relatively higher device gain, greater IC density, a self-aligned Schottky gate, controllable minimum series resistance, a relatively short channel using a conventional photo process, and a n- resistor that may be easily simultaneously fabricated therewith.
    Type: Grant
    Filed: April 27, 1978
    Date of Patent: March 3, 1981
    Assignee: Xerox Corporation
    Inventors: Keming Yeh, James L. Reuter
  • Patent number: 4251908
    Abstract: A method of fabricating the measuring junction of a grounded-junction sheathed thermocouple to obtain fast time response and good thermal cycling performance is provided. Slots are tooled or machined into the sheath wall at the measuring junction, the thermocouple wires are laser-welded into the slots. A thin metal closure cap is then laser-welded over the end of the sheath. Compared to a conventional grounded-junction thermocouple, the response time is 4-5 times faster and the thermal shock and cycling capabilities are substantially improved.
    Type: Grant
    Filed: January 15, 1979
    Date of Patent: February 24, 1981
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: Kenneth R. Carr
  • Patent number: 4249299
    Abstract: Electrical connection is made to circuits in a silicon die from its bottom surface through vacuum deposited contacts formed around one of its edges.
    Type: Grant
    Filed: March 5, 1979
    Date of Patent: February 10, 1981
    Assignee: Hughes Aircraft Company
    Inventors: Craig P. Stephens, James C. Rill
  • Patent number: 4246692
    Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor elements are beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. Resistors of this type are ideally suited for load devices in static RAM cells.
    Type: Grant
    Filed: May 28, 1976
    Date of Patent: January 27, 1981
    Assignee: Texas Instruments Incorporated
    Inventor: G. R. Mohan Rao
  • Patent number: 4244097
    Abstract: The specification describes a Schottky-gate field-effect transistor and related fabrication process wherein thin ion implanted surface stabilization regions are formed between source and gate electrodes and gate and drain electrodes of the device and to a thickness of between 100 and 1,000 angstroms. This is accomplished utilizing the source, gate and drain electrodes as an ion implantation mask against impinging inert ions which render the implanted regions semi-insulating, and this process requires no postimplantation annealing.
    Type: Grant
    Filed: March 15, 1979
    Date of Patent: January 13, 1981
    Assignee: Hughes Aircraft Company
    Inventor: Frederick W. Cleary
  • Patent number: 4242791
    Abstract: Disclosed is a method for fabricating very high performance semiconductor devices, particularly bipolar-type transistors having a heavily doped inactive base and a lightly doped narrow active base formed by ion implantation. In order to prevent the high dose boron implantation, for an NPN transistor, from getting into the active base region, a self-aligned mask covering the emitter contact i.e., active base region, is required for inactive base implantation. The self-aligned mask is anodically oxidized aluminum pads. The device wafer metallized with blanket aluminum film is immersed in a dilute H.sub.2 SO.sub.4 solution electrolytic cell which selectively anodizes only the aluminum lands situated over the Si.sub.3 N.sub.4 /SiO.sub.2 defined device contact windows. The aluminum oxide formed by anodization process is porous but may be sealed and densified. The aluminum film that is not anodized is then selectively etched off using either chemical solution or sputter etching.
    Type: Grant
    Filed: September 21, 1979
    Date of Patent: January 6, 1981
    Assignee: International Business Machines Corporation
    Inventors: Cheng T. Horng, Harold V. Lillja, David K. Seto
  • Patent number: 4241493
    Abstract: The solar cell module of this invention is fabricated by placing an array of solar cells in a suitable mold having a bottom surface, an entry port and an exit port. A light transparent superstrate effectively serves as the top for the mold and is placed over the array of solar cells in the mold. The superstrate is spaced from the array such that the superstrate does not come in contact with the top surface of any of the cells or interconnectors of the solar cell array. Clamp means are provided to hold the superstrate in position while encapsulant is pumped into the mold under pressure through the inlet port in an amount sufficient to fill the mold. Thereafter the assembly can be placed in an oven and heated for a time sufficient to cure the encapsulant and bond the materials to each other.
    Type: Grant
    Filed: December 22, 1978
    Date of Patent: December 30, 1980
    Inventors: William B. Andrulitis, Steven G. Miles, William T. Kurth
  • Patent number: 4242696
    Abstract: A method of forming a contact on the surface of a semiconductor by a serigraphy treatment in which a doped conductive paste is provided in a first deposition, and then a second deposition containing no dopant is provided at least partly on the first deposition. Devices made in accordance with the invention are particularly suited for use as photovoltaic converters for solar radiation.
    Type: Grant
    Filed: December 11, 1978
    Date of Patent: December 30, 1980
    Assignee: U.S. Philips Corporation
    Inventors: Daniel Diguet, Gerard A. David, Pierre Aubril
  • Patent number: RE30652
    Abstract: This invention relates to a method for constructing a thermoelectric module, as well as to the module so obtained. The method according to the invention comprises the steps of construction a reference shoulder on the semiconductor bar, assembling the semiconductor bars in series by using an insulating cement, cleaning the surfaces, gold plating, nickel plating, brasing copper electrodes, machining the regions between the elements which have to remain insulated, protecting the copper electrodes by nickel or chromium plating. The thermoelectric module so obtained consists of a matrix of semiconductor elements with all the mechanical and electrical connections incorporated, including the input and output terminals.
    Type: Grant
    Filed: December 13, 1978
    Date of Patent: June 16, 1981
    Assignee: Snamprogetti S.p.A.
    Inventors: Giovanni Germano, Francesco Losciale, Roberto Falesiedi, Ferruccio Daclon, Nicola Merzagora