Abstract: A method for the production of metal-semiconductor field effect transistors (MESFET) is described. Practice of the method allows one to produce self-aligning MESFETs with Si sources and drains in close proximity having metal gates therebetween.

Abstract: This invention provides the structure for a two-phase charge coupled storage device. Alternate regions of thicker and thinner silicon dioxide are grown upon a silicon substrate. These silicon dioxide regions are covered with a layer of deposited, undoped polysilicon. A layer of silicon dioxide is grown over the polysilicon. Ion implantation is applied to cause isolated regions of conductivity in the polysilicon. Then contact windows are cut in the upper most layer of silicon dioxide exposing the polysilicon therethrough and a metal coating is deposited in the contact windows. Two-phase signals are applied to the resulting electrodes to advance charges at the surface of the silicon substrate.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliabilty. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.

Abstract: A silicon body (10) of a first conductivity type is covered with a sandwich of silicon dioxide (12), polycrystalline silicon (14) and silicon nitride (16). Source, drain, and interconnect work sites of the body are exposed by a first photoshaping operation. The work sites are doped forming regions (21, 22, 23) of a second conductivity type. Silicon dioxide (24, 26, 28) is grown over the work sites. A second photoshaping operation provides an opening 36. The walls of the opening 36 on two opposite sides comprise sides of the sandwich layer as established by the first photoshaping operation and the two remaining walls comprise sides of the silicon dioxide as established by the second photoshaping operation. Silicon nitride (44) is next deposited over the entire wafer (15) which is then photoshaped to define the field regions (46, 48). The etching process is continued to remove part of the silicon body as well as the sides of those exposed regions.

Abstract: A novel semiconductor configuration is presented utilizing a narrow, gate-like (base) structure formed of, for example, a floating polycrystalline silicon line, that is capable of modulating both the number and type of carriers (electrons or holes) flowing thereunder, between a pair of similarly doped, separated regions. One particular structure described is a four terminal I.sup.2 L configuration where the inverter transistor can function in either the mode of an MOS device or the mode of a bipolar device.

Abstract: This invention relates to a method for constructing multispectral infrared detectors formed by three HgCdTe photovoltaic elements disposed in the form of a sandwich. According to the invention, each photovoltaic element is constructed by preparing a suitable slice of HgCdTe, by polishing the faces of said slice, by chemically attacking the slice, by heating the slice in the presence of mercury inside a test tube within a furnace having a suitable temperature profile, by constructing the ground contact by catalytic deposition of gold, by cementing the slice onto a support, by depositing a layer of photoresist on the slice, by masking the photoresist with the exception of a small exposure region, by eliminating the photoresist in the exposure region, by grafting the slice and by depositing the upper contact and an entire flecting layer. The individual elements are finally assembled and electrically connected to output terminals.

Abstract: A two-phase buried-channel charge coupled device wherein a doped layer of first type conductivity is formed with a predetermined doping concentration under a surface of a semiconductor body of second type conductivity. A first plurality of electrodes is formed in spaced relationship on the surface over the doped layer. Particles generating the first type conductivity are ion implanted into regions of the doped layer between the first plurality of electrodes, increasing the doping concentration of the portion of the doped layer disposed beneath such spaced regions. A second plurality of electrodes is formed over the increased concentration portions of the doped layer. The first plurality of electrodes provides the transfer gates of the device and the second plurality of electrodes provides the storage gates for the device.

Abstract: A three mask method is provided for making a field effect transistor which includes the use of a first mask for defining first and second spaced apart diffusion regions, each having first and second ends, a second mask for defining a contact region at the first end of the first and second diffusion regions and for defining a protected region at the gate region and source and drain electrodes of the transistor, the protected region extending between the second ends of the first and second diffusion regions, and a third mask for forming a gate electrode within the protected region and contact electrodes in the contact region. The source and drain electrodes are formed between the gate electrode and the first and second diffusion regions by ion implantation techniques.

Abstract: A method of making MOS devices, primarily in integrated circuit form, is disclosed. Device areas first are defined on a silicon semiconductor chip, typically by means of a silicon nitride pattern 13A-13B. This pattern then is used to locate impurity introductions and to define areas of semiconductor surface portion removal. The latter operation produces mesas 16-17 coincident with the device areas. By this combination of steps and silicon oxide regrowth 27 where silicon has been removed, well-defined conductivity type zones are formed under the silicon oxide portions to function as buried terminal zones 28, 29, 30 of MOS devices. In the sole critical mask registration step, one edge 38 of the gate electrode 31 is located relative to the boundary 39 of a buried terminal zone 28. Finally, the channel zone 34 and the other terminal zone 33 of an MOS transistor are emplaced by a self-alignment process, followed by a heating step which adjusts final device dimensions.

Abstract: An N-channel MOS integrated circuit device having a composite metal gate structure which has improved temperature stability. The gate structure uses a polysilicon layer to separate the conventional metal gate from the conventional underlying gate oxide. The metal gate and the polysilicon layer extend laterally at least to the lateral extent of the gate region. This composite metal gate structure improves the temperature stability of the IC, and may be used, for example, in read-only memory (ROM) applications. The polysilicon layer is formed without additional photolithographic steps.

Abstract: A field effect transistor is fabricated by forming a silicon dioxide film having a region where said silicon dioxide film becomes thinner at that area on one surface of a silicon semiconductor substrate of a first conductivity type at which the field effect transistor is to be formed. On said silicon dioxide film there is deposited a polycrystalline silicon layer which has an impurity concentration higher than that of the silicon semiconductor substrate. The polycrystalline silicon layer is removed by selective etching so as to leave only a part which becomes a gate of the field effect transistor.

Abstract: A programmable read only memory array of the fusible link type employs a small part of a deposited metal film as a fuse. The film is covered by a protective glaze which seals the surface of the semiconductor chip to avoid deterioration of the transistors or other components. In order to minimize heat loss to the semiconductor substrate when programming, and to provide a cavity beneath the protective glaze, the metal film is raised above the surface at the position of the fusible link. This is accomplished by a segment of photoresist applied prior to metal deposition, then removed with photoresist stripper after the metal is patterned.

Abstract: A semiconductor pressure transducer includes a base member fabricated from n-type silicon. The base member has a central depression defining an active area and located on a bottom, surface; diffused in the top surface, is at least one contact area which is directed from the active region towards the periphery of said base member. A piezoresistive sensor is located on said top surface and in contact with said contact area within said active region. A layer of epitaxial material surrounds the active region and has an aperture on the surface which is in communication with the contact area outside said active region. The epitaxial layer is polished at a top surface and a housing is coupled to the region by means of a suitable bond. Alternate methods of fabricating the transducer are shown employing both polycrystalline and monocrystalline epitaxial layers.

Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.

Abstract: A process for selectively modifying the electrical characteristics of selected MOS devices in an integrated circuit, such as in programming a read-only memory, at or near the final stage of circuit fabrication, includes the formation of a photoresist layer over the passivation layer of a nearly completed structure. Relatively narrow openings are formed in the photoresist at those locations at which it is desired to modify the underlying MOS devices, and wider openings are formed over the locations of bonding pads. Ion implantation is carried out through the narrow openings in the photoresist layer--the photoresist acting as an implantation barrier--to modify the underlying MOS devices. An oblique angle ion milling procedure is carried out in which the walls of the photoresist layer shield the passivation layer exposed by the narrow openings in the photoresist layer so as to remove the exposed portion of the passivation layer only over the bonding pad locations. The photoresist layer is subsequently removed.

Abstract: Temperature gradient zone melting is utilized to make a solid state neuron which mimics the conducting nerve pulses by a biological nerve cell and its nerve fiber.

Abstract: A plurality of porous valve-metal pellets are suspended by their anode riser wires from a holding bar. After the conventional steps of anodically forming an oxide film over the surfaces of the pellets and depositing a solid electrolyte and a metallic counterelectrode over the film, an insulative resin layer is applied over the pellets by an electrostatic fluidized powder-bed coating step, selective air-stream powder-removal steps and heat curing steps. Anode and cathode end cap terminals are subsequently formed over opposite ends of each pellet, preferably by applying and curing a silver loaded paint, curing the paint, nickel immersion plating over the silver and cladding the nickel film with solder.

Abstract: There are provided a semiconductor device having alternately layered insulating and conductive layers on the major surface of a semiconductor body and the process for manufacturing the semiconductor device. In the manufacturing process, the conductive layers other than the conductive layer finally formed are each formed to be a laminate including at least two metal layers of which the etching rates are different. The photo-engraving process follows this step. In the lamina, the metal layer closer to the semiconductor body has a lower etching rate than that of the metal layer formed thereover. In the semiconductor device, the conductive layer other than that disposed furthest away from the semiconductor body has its side wall diverged to widen toward the semiconductor body.

Abstract: A vertical insulated gate field effect transistor having a first first conductivity layer, a second second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction.The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continue the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.