Abstract: A dielectric-isolated PNP transistor with Schottky protection, either alone or as one of an integrated pair of complementary bipolar transistors has complete dielectric isolation from neighboring devices and from the substrate by means of a topside anisotropic etch. This leaves the devices in mesa form, thinner versions having the facility of lateral terminations, e.g. for the collector. The method is advantageously adapted to provide single type or complementary bipolars with integrated Schottky barrier protection.

Abstract: A solid electrolytic capacitor has an anode which consists of a sintered tantalum member having a dielectrically effective oxide layer located thereon and a counterelectrode consisting of semiconducting manganese dioxide. An anode wire is coated with polytetrafluorethylene in the vicinity of the point it enters the sintered member. In a method for producing such an electrolytic capacitor, the anode wire is brushed with a suspension containing the polytetrafluorethylene in a solvent in the vicinity of the wire entry point, before the manganese dioxide layer is produced, and the suspension is burnt-in for annealed after such application, where annealing occurs at a temperature of approximately 300.degree. C. over a period of time of approximately ten minutes.

Abstract: A method for fabricating a semiconductor device includes the formation of a monitoring element in a substrate. The monitoring element has substantially the same structure and size as a circuit element on the device which is to be monitored. Polycrystalline electrodes are contacted to the semiconductor regions of the monitoring element and extend on an insulating film covering the surface of the substrate. The electrical characteristics of the monitoring element are measured by contacting probes of a measuring apparatus to portions of the polycrystalline electrodes.

Abstract: A method of fabricating semiconductor components having electrodes and terminals. The method includes preparing an undivided semiconductor wafer having at least one pn-junction; etching a grid pattern of grooves into at least one side of the undivided wafer, thereby forming mesas with concave side surfaces and elevations with upper surfaces bounded by closed rounded curves; coating the exposed lateral surfaces of the etched mesas with a passivating layer; metallizing the upper surfaces of these elevations, thereby providing ohmic contacts for the undivided semiconductor wafer; and breaking the undivided semiconductor wafer into individual semiconductor chips along the lines of the etched grooves.

Abstract: The method of forming an MNOS transistor having a stepped channel oxide region utilizes intentional undercutting of the oxide in the channel region to provide a self-aligned mask for ion implanting a region of the same conductivity type, but more heavily doped which will be centrally located beneath the thin portion of the channel region in order to increase the threshold window of the device while saving a photomask operation.

Abstract: The method of forming an MNOS transistor having a stepped channel oxide region utilizes intentional undercutting of the oxide in the channel region to provide a self-aligned mask for ion implanting a region of the same conductivity type, but more heavily doped which will be centrally located beneath the thin portion of the channel region in order to increase the threshold window of the device while saving a photomask operation.

Abstract: A field effect transistor having a gate on the bottom of a groove in a body of semiconductor material with the source and drain being on a surface at opposite sides of the groove is made by first forming a recess in the surface of the semiconductor body. A metal layer is then coated on the surface of the semiconductor body and on the surfaces of the recess. A layer of a photoresist is then coated over the metal layer. The photoresist is then exposed to a beam of light whose rays extend along a path which is at a very small angle with respect to the surface of the semiconductor body to fully expose a narrow portion of the photoresist layer at one edge of the recess. The fully exposed portion of the photoresist layer is removed to expose a narrow area of the metal layer along the edge of the recess. The exposed portion of the metal layer is then removed and a groove is formed in the portion of the surface of the semiconductor material exposed by removing a portion of the material layer.

Abstract: A process for constructing self-aligned electrodes overlying a surface of a semiconductor substrate is disclosed. The process utilizes a substrate which is substantially transparent to infrared radiation. One step of the process includes forming spaced apart ones of the electrodes with a conductive material that is highly absorbtive of infrared radiation. Subsequently, a continuous layer of heat sensitive polymer is formed over and between these spaced apart electrodes. The resulting structure is exposed to infrared radiation which heats the spaced apart electrodes. This heat polymerizes the heat sensitive polymer layer in all regions that directly overlie the spaced apart electrodes. These polymerized regions form a mask that is used to construct other electrodes between and in alignment with the spaced apart electrodes.

Abstract: The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implanatation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and self-aligned contacts for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different oxidation and etch characteristics permits selective oxidation of only desired portions of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. The process and resulting structure affords inherently self-aligned gates and contacts for FET devices and conducting lines.

Abstract: A low-cost dye-sensitized Schottky barrier solar cell comprised of a substrate of semiconductor with an ohmic contact on one face, a sensitizing dye adsorbed onto the opposite face of the semiconductor, a transparent thin-film layer of a reducing agent over the dye, and a thin-film layer of metal over the reducing agent. The ohmic contact and metal layer constitute electrodes for connection to an external circuit and one or the other or both are made transparent to permit light to penetrate to the dye and be absorbed therein for generating electric current.

Abstract: A semiconductor integrated circuit device of the beam lead type having a semiconductor interconnection substrate with apertures for integrated circuit chips therein and with metallization patterns having sharply pointed ends for penetrating oxide layers over the bonding pads of the chips and for making electrical connection thereto. Devices thus produced may be assembled and tested and failed chips replaced as necessary before the chips are ultrasonically welded to the interconnection metallization and before final fabrication of the device. The invention also includes a method for producing an interconnection substrate in which a plurality of conically shaped holes are etched into a semiconductor wafer having sharp points within the body of the wafer. A metal layer is deposited over the surface of the semiconductor wafer filling the etched holes. Sharp points are thus formed on the metal in the etched holes.

Abstract: A solid state imaging device is formed of a bulk of monocrystalline silicon which has been suitably doped. A transparent layer of SiO.sub.2 overlays the bulk silicon, and atop the SiO.sub.2 layer is at least one pattern of doped SiC electrodes. Successive patterns of SiC electrodes are insulated from each other by SiO.sub.2. The SiC and SiO.sub.2, being derivatives of silicon, passivate the bulk and serve, respectively, as transparent electrodes and transparent support for such electrodes.

Abstract: A double-sided mosaic focal plane for infrared detection includes a semiconductor substrate having first and second opposing surfaces. Infrared detectors are mounted on the first surface and solid state signal processing circuitry is formed in the semiconductor substrate proximate the second surface. Interconnect means extend through the semiconductor substrate to interconnect the infrared detectors with the solid state signal processing circuitry.

Abstract: A plastic encapsulated integrated circuit (IC) package is disclosed which includes a conical depression or dimple precisely located over a photo-responsive semiconductor element incorporated within said integrated circuit for performing a predetermined function. The IC is encapsulated in a clear, two-part epoxy moulding compound preferably Hysol MG-18 having a tapered small depression positioned to register with the photo element but stopping short of actually touching the semiconductor photo element.Thus, the bottom of the tapered depression consists of a transparent window of sufficient thickness to protect the semiconductor element and still provide optical coupling. The minimum diameter of the light input depression located preferably at the top of the clear plastic package is designed to receive a snug fitting light pipe of Lucite or other clear material that could be used as a fiber optic element.

Abstract: An array of porous oxide-filmed tantalum pads that are sintered to a tantalum foil, each have a composite MnO.sub.2 layer formed thereover by the steps of filling the pad pores with a manganous nitrate solution by capillarity from a sponge-like reservoir pressed gently against the pads, pyrolyzing, screen printing over the first MnO.sub.2 sublayer a thixotropic mixture of MnO.sub.2 powder and manganous nitrate and pyrolyzing, and again depositing from the sponge-like reservoir a quantity of manganous nitrate and pyrolyzing again. A counterelectrode is formed over the composite MnO.sub.2 layer at the top of each pad. A temporary masking layer is deposited over each of the counterelectrodes. The streets separating the pads, and the pads themselves are flooded with an insulative resin. Excess resin is removed with a squeegee and the resin is cured. The masking layer is removed and slots are gouged in the resin in the alternate of the columnar streets, which alternate streets are wider than the others.

Abstract: The semiconductor device comprises a semiconductor substrate, a polycrystalline silicon semiconductor body extending upwardly from a portion of the surface of the semiconductor substrate and containing an impurity at a substantially uniform concentration, and a metal electrode disposed on the top surface of the polycrystalline silicon semiconductor body. The metal electrode extends in the lateral direction beyond the periphery of the top surface of the polycrystalline silicon semiconductor body.

Abstract: A cell for a semiconductor memory of the static type employs two conventional MOS transistors along with a field implanted resistance which functions as a grounded-gate junction FET. Along with other resistor elements, these devices provide a grounded-gate amplifier with voltage gain and a source follower, creating a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.

Abstract: A semiconductor die having bump type contact areas thereon with film strip leads bonded thereto and fired glass encapsulating only the active side of the die and the bump contact areas. The method of encapsulation includes bonding the film strip leads to the bumps of the die, coating the bumps and active area with unfired glass and firing the glass at a temperature generally below 450.degree. C. The method also includes bonding the film strip leads to the bumps and firing the glass simultaneously or firing the glass and remelting glass covering the bumps to bond the leads to the bumps through the fired glass.

Abstract: In a monolithic integrated circuit having a combination of bipolar and junction field effect transistors, a pulsed laser is employed to trim the transistors to achieve balanced circuit performance. The laser is applied to individual circuits in wafer form using a step and repeat operation. Each circuit is measured, the transistor to be trimmed determined and a first trim performed. The circuit is remeasured and, if still out of specification, retrimmed. The process is repeated until a desired degree of balance is achieved.