Abstract: A memory in which each cell comprises an MOS transistor merged with a storage capacitor and in which the cells are arranged to permit adjacent pairs of transistors in a common column to share a common source and the transistors in a common row to share a common gate electrode conductor. The memory uses a first polycrystalline silicon layer which is patterned to provide interconnected storage electrodes and a second polycrystalline silicon layer which is patterned to provide a plurality of stripes to serve as the bit sense lines and a plurality of gate electrodes.

Abstract: In a two-level overlapping polysilicon device even the slightest amount of undercutting of an oxide layer (12) which underlies a first polysilicon layer (14) can lead to unacceptably low breakdown voltages in the device. In accordance with the invention, the first polysilicon and oxide layers of an LSI MOS wafer are defined as usual. But then the standard fabrication process is modified to etch the first polysilicon layer back beyond the edge of the oxide undercut. Subsequently, the structure is reoxidized and a second polysilicon layer (22) deposited and patterned. The modified process is characterized by the absence of any oxide thinning between the first and second polysilicon layers or between the second polysilicon layer and the substrate (10) of the device. As a result, voltage breakdown problems in the individual chips of the wafer are thereby greatly reduced and the yield of the wafer significantly increased.

Abstract: Thick double heterostructure (Al,Ga)As wafers comprising layers of gallium arsenide and gallium aluminum arsenide on a metallized n-GaAs substrate are separated into individual devices for use as diode lasers. In contrast to prior art techniques employed with thinner wafers of mechanically cleaving the wafer in mutually orthogonal directions, the wafer is first separated into bars of diodes by a process which comprises (a) forming channels of substantially parallel sidewalls about 1 to 4 mils deep into the surface of the n-GaAs substrate (b) etching into the n-GaAs substrate with an anisotropic etchant to a depth sufficient to form V-grooves in the bottom of the channels and (c) mechanically cleaving into bars of diodes. The cleaving may be done by prior art techniques using a knife, razor blade or tweezer edge or by attaching the side of the wafer opposite to the V-grooves to a flexible adhesive tape and rolling the assembly in a manner such as over a tool of small radius.

Abstract: A semiconductor wafer is appropriately doped to create a P-N or P-I-N junction, and metallized on both its planar surfaces with electrode material. The wafer is then bonded to a second similarly processed wafer. Without damaging the semiconductor material, the stacked wafer is processed so as to delineate a plurality of diodes on each side of the center metallization, such that the diodes on each side are registered with each other. The center metallization is then cut so as to yield a plurality of stacked semiconductor diodes.

Abstract: Double heterostructure (Al,Ga)As wafer comprising layers of gallium arsenide and aluminum gallium arsenide on a metallized n-GaAs substrate are separated into individual devices for use as diode lasers. In contrast to prior art techniques of mechanically cleaving the wafer in mutually orthogonal directions, the wafer is first separated into bars of diodes by a process which comprises (a) forming an array of exposed lines on the n-side by photolithography to define the lasing ends of the diodes, (b) etching through the exposed metallized portion to expose portions of the underlying n-GaAs, (c) etching into the n-GaAs substrate with a V-groove etchant to a distance of about 1 to 2 mils less than the total thickness of the wafer and (d) mechanically cleaving into bars of diodes.

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions.

Abstract: In a semiconductor integrated circuit device composed of insulated gate field-effect transistors, the improvement comprises the fact that insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix. Gate input columns of the transistors are formed of polycrystalline silicon layers, and some of the transistors are enhancement type, while others are depletion type. Further, the respective transistors are formed by the self-alignment technique which employs the polycrystalline silicon layers as a diffusion mask, and the depletion type transistors are formed by implanting impurity ions opposite in the conductivity type to the substrate into selected areas of the surface of the substrate. Thus, a read only memory in a MOS-IC chip has its occupying area reduced remarkably.

Abstract: Powdered plastic encapsulation of solid tantalum capacitors is achieved through coating the capacitors between 150.degree. C. and 250.degree. C. while biasing the capacitors at direct voltage between 0.2 and 1 times the rated voltage. The plastic is cured in about 3 minutes. The capacity temperature derating and the reverse current temperature derating are reduced with respect to capacitors encapsulated unbiased at the same temperature.

Abstract: A method for fabricating a field-effect transistor device is provided with the device resulting having a relatively substantial capability to withstand reverse bias voltages. The device can also be provided having a relatively low "on" condition resistance between the source and drain terminals thereof by virtue of a geometrical design choice.

Abstract: A semiconductor layer different in material from a semiconductor substrate formed on at least one part of the surface of the substrate is partially removed in accordance with a planar configuration forming technique employing irradiation of a radiation such as light, electron beam or X-rays to form a residual layer and ion beams are applied to the upper surface or the substrate at an incidence angle less than 90 degrees so that a non-etching region is formed at the region of the substrate other than the region around and beneath said residual layer according to mutual relationships between the configuration of the residual layer and the incidence angle of the ion beams.

Abstract: A contact structure to the light emitting surface 19 of a light emitting device 10 having an array of small distributed contacts 14 is made by selectively depositing a larger area bonding pad 15 over a portion of the distributed contacts. The small contacts not covered by the bonding pad then are removed by sputter etching and contact to the device is made by wire bonding a lead 17 to the bonding pad.

Abstract: A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for diffused conducting lines in the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having oxidation and etch characteristics permits selective oxidation of desired portions only of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. There results semiconductor devices of minimum geometry with selective interconnection capabilities, affording VLSI circuits having increased density with improved yield and reliability.

Abstract: A method of fabricating very large scale integrated circuits including N-channel silicon gate nonvolatile memory elements and additional peripheral transistor elements. The nonvolatile memory elements are fabricated as PDS protected drain-source devices composed of a variable threshold memory device having a thin silicon dioxide gate insulator in combination with a pair of fixed threshold devices having a thicker silicon dioxide gate insulator arranged with a common silicon nitride layer and common gate electrode. The additional fixed threshold peripheral transistors are fabricated without a silicon nitride layer. In addition, the method contains no processing steps subsequent to the fabrication of the PDS devices which necessitate the application of temperatures in excess of 900.degree. C.

Abstract: A method for producing semiconductor bodies having a glass covered defined dge profile from a semiconductor wafer comprising the steps of applying etch resistant protective coating to a surface oxide layer on the semiconductor wafer, cutting groove-shaped recesses in the wafer in a predetermined pattern, etching the wafer through the recesses to produce a deep portion passing through at least one pn-junction, removing the surface oxide layer and etch resistant coating, applying an insulating and stabilizing glass coating to the side faces of the deep portion of the wafer, applying a contact metal coating, dividing the wafer into semiconductor bodies along the center planes of selected deep portions of the wafer and covering the surface of the semiconductor bodies with an insulating lacquer at those portions which have been exposed by the dividing step.

Abstract: For the production of V-MOS single transistor storage cells at the surface of a silicon crystal of first conductivity type, two adjoining zones of opposite conductivity type can first be produced by masked diffusion or implantation. Then, with the use of a correspondingly oriented etching mask, a funnel-shaped depression is produced at the semiconductor surface such that the two zones of opposite conductivity type are separated from one another but reach the surface of the silicon crystal within the funnel-shaped depression. This depression is then coated with a thin SiO.sub.2 layer which is provided as a carrier of the gate electrode of the field effect transistor which forms the storage cell. The two zones of the opposite conductivity type, now separated, are used as a source and as a drain and also as a storage capacitance. For geometric reasons, the two zones of opposite conductivity type can only be produced one after the other with the use of corresponding doping masks.

Abstract: An energy efficient process is disclosed for the continuous production of semiconductor matrices formed from depositing doped silicon or germanium films on metallic sheet substrates. The energy released from such deposition can then be used to regenerate the anode material used in the deposition.

Abstract: A method for use in making semiconductor type electrical devices such as solar cells. In the method, a wafer of semiconductor material having two major surfaces is provided, the wafer being doped with an impurity of one conductivity type. A layer of a metal-containing compositions such as aluminum, is placed on one of the major surfaces of the wafer, and the wafer is then heated in the presence of an impurity of the opposite conductivity type to a temperature such that a high-low junction is formed by the metal at one major surface while the impurity of the opposite conductivity type diffuses or penetrates the other major surface to form a p-n junction thereat.

Abstract: Ions are implanted into a body, such as semiconductor substrate material, through one or more covering layers formed over the body. A thin conductive film is in contact with the covering layer prior to the ion implantation. The ions are implanted into the material through the thin conductive film. The conductive film functions to conduct away any charge which tends to accumulate in the covering layer. The conductive film thereby prevents a charge accumulation which would tend to discharge through and cause damage to the covering layer. The method is particularly useful for fabricating MOS and CMOS semiconductor devices.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component with low electrical and thermal impedances is provided. The semiconductor component includes a thin semiconductor device with a plurality of layers of various conductivity types forming the active regions and semiconductor/metallic transition layers. The low electrical impedance of the component is achieved by the use of the thin semiconductor device, while the low thermal impedance is provided by a thick pedestal metalization on the semiconductor device.The method for manufacturing such a device includes the fabrication of at least one semiconductor device on one surface of a semiconductor substrate. The second surface of the semiconductor substrate is selectively etched by a controlled process to form a cavity of limited lateral extent adjacent to each of the semiconductor devices on the one surface.