Patents Examined by W. G. Saba
  • Patent number: 4502898
    Abstract: A process is described for doping compound semiconductors using a metal fluoride (e.g., ZnF.sub.2) as the source of dopant. The anhydrous metal fluoride is put down on the surface of the compound semiconductor, capped with a suitable encapsulant and heat treated to promote the diffusion. The heat treatment can be carried out in air without danger of surface damage to the compound semiconductor. Also, the diffusion is better controlled as to depth of diffusion and boundary delineation.
    Type: Grant
    Filed: December 21, 1983
    Date of Patent: March 5, 1985
    Assignee: AT&T Bell Laboratories
    Inventors: Irfan Camlibel, Howard J. Guggenheim, Shobha Singh, LeGrand G. Van Uitert, George J. Zydzik
  • Patent number: 4497665
    Abstract: In a method of fabricating a semiconductor device having a V-groove insulating isolation structure with polycrystalline silicon filled in the groove of which the internal surface is covered with an insulating film of silicon dioxide, the method according to this invention comprises the steps of selectively ion implanting an impurity material into a desired region of the polycrystalline silicon layer in order to give to this region a desired different type of electric conductivity relative to the polycrystalline silicon layer followed by a selective annealing by an energy beam such as a laser of a desired part of the polycrystalline silicon layer including the region into which the impurity material has been ion implanted.
    Type: Grant
    Filed: January 3, 1983
    Date of Patent: February 5, 1985
    Assignee: Fujitsu Limited
    Inventor: Takeshi Fukuda
  • Patent number: 4481707
    Abstract: The process of fabricating a dielectrically isolated junction field effect transistor and a PNP transistor on a common substrate. An epitaxially layer is deposited on the base substrate to form the channel region of the junction field effect transistor. Impurities for the source and drain of the field effect transistor are diffused into the epitaxial layer. Impurities to form the gate are diffused into the epitaxially layer between the source and gate regions but separated therefrom. The PNP transistor which is dielectrically isolated from the field effect transistor by grooves, is formed by the diffusion into the base substrate of the respective impurities that form the base, collector and emitter regions of the PNP transistor.
    Type: Grant
    Filed: February 24, 1983
    Date of Patent: November 13, 1984
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Kevin F. Cunniff
  • Patent number: 4476623
    Abstract: This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.
    Type: Grant
    Filed: July 1, 1981
    Date of Patent: October 16, 1984
    Assignee: International Business Machines Corporation
    Inventor: Badih El-Kareh
  • Patent number: 4468852
    Abstract: Two patches of silicon nitride are formed above spaced-apart regions of an n-type substrate (2) on an overlying oxide layer (8) of small thickness. Arsenic ions are then implanted through the oxide layer in substrate areas not covered by the patches whereupon one patch (10a) and an adjoining portion of the oxide layer are covered by a masking layer (15) of polycrystalline silicon, leaving unprotected the second patch (10b) and an oxide portion adjacent thereto. The wafer is then bombarded with boron ions, first at a relatively low concentration and high energy level to penetrate the oxide layer as well as the second patch (10b) and then, after an intervening high-temperature heat treatment in a nonoxidizing atmosphere, at a relatively high concentration and low energy level. This results in the formation of a p-well (17) bounded by an n+ guard zone (23) and partly underreaching same, with an exposed area of that guard zone converted to p+ conductivity by the second-stage boron bombardment.
    Type: Grant
    Filed: April 5, 1983
    Date of Patent: September 4, 1984
    Assignee: SGS-Ates Componenti Elettronici S.p.A.
    Inventor: Gianfranco Cerofolini
  • Patent number: 4466172
    Abstract: A method for fabricating an integrated circuit semiconductor device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer (30) surrounding openings (99) therein for the MOSFET elements. A gate electrode (38) within each opening is utilized to provide self-registered source (42) and drain (44) regions and is covered on all sides and on its top surface with a gate dielectric layer (46). After the formation of the source-drain regions a relatively thin dielectric protective layer (38) is applied to the entire chip prior to the application of an upper insulative layer (50).
    Type: Grant
    Filed: July 27, 1981
    Date of Patent: August 21, 1984
    Assignee: American Microsystems, Inc.
    Inventor: Tarsaim L. Batra
  • Patent number: 4466173
    Abstract: Methods for fabricating vertical channel buried grid field controlled devices with improved performance characteristics include methods which avoid the problems caused by autodoping effects. In one form of the invention, one surface of a semiconductor substrate is preferentially etched to form substantially vertically-walled grooves, and the grooves are selectively refilled employing vapor phase epitaxial growth to form a grid structure. A semiconductor layer is then epitaxially grown over the substrate surface and grid so as to bury the grid. In another form of the invention, grooves are preferentially etched in semiconductor substrate to achieve steep vertical walls. Thereafter, the grooves are either partially refilled by means of epitaxial growth or, preferably, completely refilled and then again preferentially etched to remove a predetermined fraction of the refilling. A second epitaxial refill is done to fill the remainder of the grooves.
    Type: Grant
    Filed: November 23, 1981
    Date of Patent: August 21, 1984
    Assignee: General Electric Company
    Inventor: Bantval J. Baliga
  • Patent number: 4466171
    Abstract: A method of manufacturing a semiconductor device having two juxtaposed regions (12, 16) of opposite conductivity types which adjoin a surface and which together constitute a p-n junction (9) which is preferably perpendicular to the surface and the doping concentration of which decreases towards the surface. According to the invention n-type and p-type buried layers (2, 6) are provided beside each other on a semiconductor substrate (1) and on said layers a high-ohmic epitaxial layer (7) is grown. By heating, the dopants diffuse from the buried layers through the whole thickness of the epitaxial layer and into the substrate. With suitably chosen donor and acceptor atoms (for example boron and phosphorus in silicon) n and p-type regions (12, 16) are formed in the epitaxial layer and form a p-n junction (9) perpendicular to the surface by compensation of the lateral diffusions from the buried layers.
    Type: Grant
    Filed: April 24, 1981
    Date of Patent: August 21, 1984
    Assignee: U.S. Philips Corporation
    Inventor: Pieter J. W. Jochems
  • Patent number: 4466180
    Abstract: The invention is a punch through voltage regulator having an active region formed on a substrate by any one of four different methods. Each method includes recessing the substrate substantially along the periphery of the regulator active region, selectively doping the regulator active region through portions of the recess, filling the recesses with substrate oxide to isolate the active region from the substrate and forming conductors to selectively doped portions of the active region to serve as electrode connections. For P doped substrates N type doping is introduced via the recesses and in a second method the recesses are deepened and P type doping is introduced into the substrate to change the doping in the active region. For N doped substrates P type doping is introduced via the recesses and when the recesses are deepened in the fourth method, N type doping is introduced into the substrate to change the doping of the active portion.
    Type: Grant
    Filed: June 25, 1981
    Date of Patent: August 21, 1984
    Assignee: Rockwell International Corporation
    Inventor: Sidney I. Soclof
  • Patent number: 4462847
    Abstract: A method for the fabrication of microelectronic semiconductor circuits, including the concurrent low pressure deposition of monocrystalline and polycrystalline semiconductor material in a predetermined pattern. In a preferred embodiment, a dielectric isolated circuit is fabricated, by such selective epitaxial growth, and a subsequent oxidation of both the mono- and polycrystalline deposits. By controlling the ratio of the deposition rates, and by controlling the oxidation step, the poly deposit is substantially fully converted to oxide, while the mono is only partly oxidized, leaving a substantially coplanar, isolated matrix of passivated monocrystalline areas in which to fabricate circuit components for interconnection.
    Type: Grant
    Filed: June 21, 1982
    Date of Patent: July 31, 1984
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen W. Thompson, Ralph Keen
  • Patent number: 4447276
    Abstract: A method of growing crystalline semiconductors such as GaAs is disclosed. The method involves epitaxial deposition from the vapor phase and provides dopant material such as sulphur in the form of a molecular beam. The molecular beam is developed by effusion from a knudsen cell. The difficulties previously encountered using sulphur as such a cell are counteracted by use of an electrochemical cell as the sulphur source. The technique allows complicated doping profiles to be produced.
    Type: Grant
    Filed: June 15, 1981
    Date of Patent: May 8, 1984
    Assignee: The Post Office
    Inventors: Graham J. Davies, Roger Heckingbottom, David A. Andrews
  • Patent number: 4445268
    Abstract: A method of manufacturing a semiconductor integrated circuit of the BI-MOS type on a common semiconductor substrate comprising forming an oxide film by thermal oxidation to isolate the elements and a base layer of one conductivity type by a surrounding dielectric followed by removing the oxide film from emitter and collector electrode extending regions. A silicon film of a second conductivity type is formed by patterning and used to form an emitter layer and a collector extending layer by differing purities from the silicon film. Patterning is then employed to form gate, emitter and collector electrodes. Finally, the mask for the silicon film is used to form a base electrode extending layer, a source layer and a drain layer of the first conductivity type and of high impurity density.
    Type: Grant
    Filed: February 12, 1982
    Date of Patent: May 1, 1984
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tadashi Hirao
  • Patent number: 4443932
    Abstract: Improved self-aligned semiconductor devices are made using two sets of superposed pattern forming layers; a master mask layer set containing the self-aligned patterns, and a pattern selector layer set which allows different apertures in the master mask layer to be selectively re-opened so that different device regions may be sequentially formed. The master mask layer is a double layer of a first material resistant to typical device forming processes, covered by a second etch stop material. The selector layer may be a single process resistant material or a double layer. Using combinations of silicon oxide and nitride, the process is applied to the formation of silicon islands with emitters and emitter, base, and collector contacts self-aligned to each other and a surrounding oxide isolation region. Significant area and cost savings are achieved without additional masking steps or precision alignments.
    Type: Grant
    Filed: January 18, 1982
    Date of Patent: April 24, 1984
    Assignee: Motorla, Inc.
    Inventors: Sal Mastroianni, Walter F. Krolikowski
  • Patent number: 4442449
    Abstract: An interconnect structure for use in integrated circuits comprises a germanium-silicon binary alloy. Such an alloy is deposited on the semiconductor wafer from the co-deposition of germanium and silicon using chemical vapor deposition techniques of a type commonly used in the semiconductor industry. The resulting alloy can be oxidized, selectively removed and doped with selected impurities to provide a conductive lead pattern of a desired shape on the surface of a wafer.
    Type: Grant
    Filed: March 16, 1981
    Date of Patent: April 10, 1984
    Assignee: Fairchild Camera and Instrument Corp.
    Inventors: William I. Lehrer, Bruce E. Deal
  • Patent number: 4435898
    Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The bipolar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitter is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter is etched. and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth.
    Type: Grant
    Filed: March 22, 1982
    Date of Patent: March 13, 1984
    Assignee: International Business Machines Corporation
    Inventors: Santosh P. Gaur, John S. Lechaton, Gurumakonda R. Srinivasan
  • Patent number: 4435895
    Abstract: A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.
    Type: Grant
    Filed: April 5, 1982
    Date of Patent: March 13, 1984
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Louis C. Parrillo, George W. Reutlinger, Li-Kong Wang
  • Patent number: 4435224
    Abstract: Process for obtaining a homogeneous layer of composition Hg.sub.1-x Cd.sub.x Te, comprising the steps of:subjecting a wafer formed by a layer of Hg.sub.1-x.sbsb.o Cd.sub.x.sbsb.o Te deposited by epitaxial growth on a CdTe substrate, x.sub.o being less than the desired value x, to a melting treatment,then rapidly cooling the wafer.
    Type: Grant
    Filed: February 17, 1981
    Date of Patent: March 6, 1984
    Assignee: Societe Anonyme de Telecommunications
    Inventor: Alain Durand
  • Patent number: 4433470
    Abstract: A method of manufacturing a semiconductor device wherein grooves are formed between vertical type-npn transistors and insulating oxide layers are formed on the bottoms of the grooves, thereby preventing parasitic p-n junctions, which is characterized in that said grooves are formed by using as a mask a conductive pattern containing an impurity for forming an impurity region or by using as a mask an insulating film formed by the annealing of the conductive pattern.
    Type: Grant
    Filed: May 14, 1982
    Date of Patent: February 28, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Shuichi Kameyama, Koichi Kanzaki, Yoshitaka Sasaki
  • Patent number: 4430793
    Abstract: A semiconductor device is fabricated by a process in which an aperture (4) is an insulating layer (3) along a surface (2) of a semiconductor body is utilized in defining the lateral extents of zones (6, 7, and 8) in a circuit element of the device. In particular, the insulating layer is first provided with the aperture along the surface. A semiconductor layer (5) is formed on the insulating layer, including the portion within the aperture. Using the edge of the insulating layer along the aperture as a masking edge, a pair of opposite-conductivity dopants are introduced selectively into the aperture and a third dopant is introduced through all of the aperture into the body. The third dopant may be introduced into the body before the semiconductor layer is formed.
    Type: Grant
    Filed: January 11, 1980
    Date of Patent: February 14, 1984
    Assignee: U.S. Philips Corporation
    Inventor: Cornelis M. Hart
  • Patent number: 4428111
    Abstract: A process for fabricating a high speed bipolar transistor is described wherein the collector, base and emitter layers are first grown using molecular beam epitaxy (MBE). A mesa etch is performed to isolate a base-emitter region, and a contact layer is grown using MBE over this isolated region to make contact with the thin base layer. The contact layer is selectively etched to expose the emitter layer, and metal is deposited to fabricate emitter, base and collector contacts.
    Type: Grant
    Filed: December 7, 1981
    Date of Patent: January 31, 1984
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Robert G. Swartz