Abstract: In an exemplary embodiment, after underetching a first polysilicon layer beneath spaced SiO.sub.2 cover layers to produce pairs of confronting SiO.sub.2 overhangs with gaps therebetween, and providing an insulating layer at the end faces of the spaced poly-Si-1 electrodes formed from the first polysilicon layer, a second polysilicon layer is produced by chemical vapor deposition (CVD) so as to fill the cavities beneath the SiO.sub.2 overhangs via the gaps between each pair of confronting overhangs. The second polysilicon layer is then etched away so as to leave intervening self-adjusting, nonoverlapping poly-Si-2 electrodes formed from the second polysilicon layer with surfaces terminating for example slightly below the upper surfaces of the SiO.sub.2 cover layers. For a center-to-center spacing of poly-Si-1 electrodes of six microns, the SiO.sub.2 overhangs may have an extent (e.g. 0.7 microns) about equal to the electrode layer thickness (e.g. 0.8 microns).

Abstract: A method of fabricating a vertical static induction semiconductor device comprising depositing a polycrystalline silicon film on a single crystal silicon layer, and forming an insulating film comprised of silicon nitride on the polycrystalline film. The insulating film is selectively etched to form islands of the insulating film overlying areas where a gate region and a main electrode region of the semiconductor device are to be formed. An oxide film is formed on the surface regions exposed by etching, and the oxide film is used as a mask for controlling introduction of impurity atoms to form the gate region and the main electrode region.

Abstract: A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of:forming on a silicon epitaxial layer (13) of n-type conductivity a doped oxide film (14) containing boron as an impurity to give p-type conductivity,forming a mask (15a, 16a) containing Si.sub.3 N.sub.

Abstract: In an exemplary embodiment, a first polysilicon layer is provided with a SiO.sub.2 mask, and the first polysilicon layer is etched away under the SiO.sub.2 mask to produce SiO.sub.2 overhangs of a lateral extent corresponding to about twice the edge position error (.sup..+-. s). Then when second polysilicon layers are produced by means of chemical vapor deposition (CVD), to occupy the cavities under the SiO.sub.2 overhangs, the desired nonoverlapping poly-Si-2 electrodes result after definition of those poly-Si-2 electrodes by known lithographical techniques.

Abstract: A method of making a Zener diode having a Zener voltage in the range of 2.4-3.3 volts. The PN junction is preferably formed by selective epitaxial deposition of P-type silicon on a previously oxidized N-type silicon wafer in an opened region where the oxide has been etched away. The N-type wafer may be a uniform silicon wafer with resistivity in the range of 0.004 to 0.006 .OMEGA.-cm or a low resistivity N-type wafer having a 5-20 .mu.m thick N-type silicon epitaxial layer with a resistivity in a range of 0.004-0.006 .OMEGA.-cm. The selectively deposited P-type layer may have a resistivity of 0.001-0.003 .OMEGA.-cm and a thickness of 1.5-3.0 .mu.m. The P-type layer is grown in a gas phase epitaxial reactor by etching the N-type wafer at a first temperature and then depositing heavily-doped silicon at a second, lower temperature.

Abstract: A method of making a silicon solar energy cell having a substantially constant voltage despite significant increases in illumination, in which the back surface junction of the cell is formed by aluminum alloying at relatively low temperatures.

Abstract: Dielectric isolation through electron beam irradiation is applied to a method of fabricating a semiconductor device. Upon forming an insulated gate field effect semiconductor device (FET) in a semiconductor layer on an insulation substrate, the insulated gate electrode is formed to extend over the semiconductor layer region around a semiconductor region in which FET is to be implemented. A semiconductor layer pattern underlying the extension of the gate electrode is enclosed by linear dielectric layers formed along the periphery of the electrode extension through electron beam irradiation. The pattern formation can be accomplished in a short time by virtue of arrangement such that the semiconductor layer pattern is enclosed by the linear dielectric layers. Electric coupling such as capacitive coupling between the gate electrode and other conductor layers is significantly reduced.

Abstract: In a process for producing a semiconductor device using an insulating substrate, a so called SOS device, a semiconductor layer is formed on the insulating film and semiconductor elements are formed in the semiconductor layer, material, which develops color with in the insulating substrate, is introduced in the substrate, and a color developed part of the insulating substrate is used as an identification mark of the substrate and the semiconductor elements. Cracking of the substrates due to formation of the identification mark is prevented.

Abstract: A Charge Coupled Device (CCD) structure employing two levels of electrode metallization. The field plate electrodes are arranged in pairs with the second one of each pair partially overlapping and insulated from the first one of its pair and the first one of the next pair. The structure can be operated two-phase or four-phase with four electrodes per bit and three-phase with three electrodes per bit by providing suitable amounts of electrode overlap and suitable drive circuitry. A particularly advantageous mode of two-phase operation with four electrodes per bit is enabled by providing asymmetrical overlapping of electrodes, the second electrode of each pair overlapping the first electrode of its pair more than the first electrode of the next pair.

Abstract: A method of fabricating a high-frequency bipolar transistor structure wherein the emitter, higher impurity concentration base, and lower impurity concentration base regions are defined in a single masking operation. Permeation etching is used to etch regions of an oxide layer under a layer of resist which defines regions of the higher impurity concentration thereby simultaneously defining the emitter and lower impurity concentration base regions. The higher impurity concentration base regions are formed by ion implantation of impurities through the unetched oxide regions. The resist is then removed and the lower impurity concentration base and emitters are formed through the resulting opening in the oxide. This results in the self-aligning of the emitter regions with respect to the base regions.

Abstract: A method of fabricating a semiconductor integrated circuit device wherein a substrate having a particular crystallographic orientation is selectively etched so as to form surface depressions of different depths. An epitaxial layer is grown from a Si--H--Cl system on the surface of the substrate having the surface depressions formed therein. The epitaxial layer is grown under conditions effective to achieve faster lateral growth than vertical growth so as to form the epitaxial layer with regions of three different thicknesses. Subsequently, additional regions of the semiconductor integrated circuit are formed in the epitaxial layer regions of different thicknesses so as to complete the device.

Abstract: A composite semiconductor/glass material comprising at least one semiconductor layer permanently connected to a plate shaped glass substrate, the doping of the semiconductor layer rising from a minimum at its surface away from the glass substrate to a maximum adjacent the glass substrate.

Abstract: An electroluminescent semiconductor device such as a semiconductor laser has epitaxial monocrystalline layers (3 to 6), including an active layer (4), grown on a substrate (2). The epitaxial layers are etched in the presence of an etching mask (8) to form nonplanar mirror surfaces (9) which in the longitudinal direction bound active regions (10). To form flat and parallel mirrors (12) an epitaxial monocrystalline protective layer (11) is grown from the gaseous phase on the mirror surfaces after etching. The etching can be carried out in two stages using different etchants. With the first etchant the etched layers taken on a swallow-tail profile and then with the second etchant they take on a concave profile.

Abstract: A method for device fabrication utilizing a self-aligned process. A combination of advanced semiconductor processing techniques including Deep Dielectric Isolation by reactive-ion etching, etching and refilling, planarizing with oxides and resists, and differential thermal oxidation are used to form devices having small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls which extend from the epitaxial silicon surface through the N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3 .mu.m. A shallow oxide trench extends from the epitaxial silicon surface to the upper portion of the N+ subcollector and separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter.

Abstract: A diffused resistor included in a Schottky device formed in a planar semiconductor material comprises a resistor diffusion formed in the surface of the material and a contact diffusion formed in the surface of the material, the configuration of the contact diffusion being essentially coincident with the shape of the resistor at the location at which ohmic contact to the resistor diffusion is made.

Abstract: A controlled environment process for making diode arrays by depositing the sublimate of a semiconductor material through an aperture of a mask placed nearby a substrate and then subjecting part of the sublimate to ion implantation. The aperture causes diffraction of the sublimate vapor stream while the proximity of the edges of the aperture to the substrate causes the central plateau of the deposited thin-film to have a rounded rim leading to sides that taper smoothly in thickness to the substrate. Ion implantation to a controlled depth creates an isolated planar junction. Surface layers of a gold electrode running onto the substrate from different surface areas of the thin-film provide for off-mesa bonding of electrical leads.

Abstract: Disclosed is an improved method of growing an epitaxial layer preventing auto-doping from a doped region exposed to a surface of a semiconductor substrate. A surface of a semiconductor substrate of one conductivity type is covered with a mask having a predetermined opening. Then, impurity atoms are doped into the substrate through the opening to form a region of the other conductivity type. An epitaxial layer of one conductivity type is deposited over the exposed surface of the substrate with another mask which covers the entire surface of the region and has an area larger than that of the exposed surface of the region. The latter mask prevents auto-doping from the region of the other conductivity type. The process is usable for controlling, for example, channel widths of field effect semiconductor devices uniformly and precisely.

Abstract: A bipolar semiconductor is manufactured by forming a plurality of grooves along the vertical (111) planes in a high resistivity epitaxial silicon layer which is disposed on an N+ (110) oriented substrate. Low resistivity epitaxial silicon of the same conductivity type is then used to fill in the grooves, thus forming alternate vertical regions of high and low resistivity. A base region is then diffused into said epitaxial layer and a plurality of emitters regions are diffused into said base region at locations directly above the low resistivity epitaxial regions.

Abstract: A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I.sup.2 L) technology. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. The first insulating layer is removed in areas designated to contain integrated injection logic devices. A layer of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit.

Abstract: Disclosed is a self-aligned process for providing an improved high-performance bipolar transistor. The transistor device region is isolated from the other devices on the wafer by a wide deep oxide trench. The deep oxide trench which has nearly vertical sidewalls, extends from the epitaxial silicon surface through the N.sup.+ subcollector region into the P.sup.- substrate. A shallow oxide trench is used to separate the collector reach through region from the base region. A heavily doped polysilicon layer is used to dope and make contact to the transistor base as well as define the emitter window through which the emitter is doped. In the structure, the separation between the emitter contact and the polysilicon base contact is reduced to a very small value. This is achieved by employing the self-aligned process in accordance with the invention. Metal contact to the polysilicon base contact is done over the deep trench oxide isolation.