Patents Examined by W. G. Saba
  • Patent number: 4255208
    Abstract: A method is described for producing semiconductor films, particularly monocrystalline silicon and germanium films, characterized by the steps of: epitaxially growing on a substrate, such as silicon or sapphire, a layer of dissolvable material, such as sodium fluoride, sodium chloride, or silver; epitaxially growing on the dissolvable layer a layer of the semiconductor; and dissolving the dissolvable layer, thereby separating the semiconductor from the substrate. The substrate may thus be reused as a matrix for growing many such films. Also a plurality of semiconductor layers may be epitaxially grown on a common substrate each separated by a dissolvable layer, all the latter layers being dissolved at one time to produce a plurality of the semiconductor films.
    Type: Grant
    Filed: May 25, 1979
    Date of Patent: March 10, 1981
    Assignee: Ramot University Authority for Applied Research and Industrial Development Ltd.
    Inventors: Siegfried G. Deutscher, Enrique Grunbaum
  • Patent number: 4255496
    Abstract: A steel wire element useful in the reinforcement of rubber compositions in which the steel wire is provided with an adhesive coating comprising a brass alloy containing 58% to 75% copper, and cobalt in an amount sufficient in use to improve the adhesion between the coated steel wire and the rubber composition. Preferably the brass alloy contains 2% to 4% of cobalt. Applications include coated steel cords for use in vehicle tires and conveyor belts and hoses.
    Type: Grant
    Filed: May 21, 1979
    Date of Patent: March 10, 1981
    Assignee: N. V. Bekaert S.A.
    Inventor: Guy Haemers
  • Patent number: 4253887
    Abstract: A method of depositing a layer of semi-insulating gallium arsenide on a substrate by vapor phase epitaxy. The layer is deposited by thermally decomposing a gaseous mixture of arsine, gallium chloride and a small amount of water vapor to deposit a layer of gallium arsenide doped with oxygen.
    Type: Grant
    Filed: August 27, 1979
    Date of Patent: March 3, 1981
    Assignee: RCA Corporation
    Inventor: Stuart Jolly
  • Patent number: 4252866
    Abstract: An electro-galvanized steel sheet for coating excellent in bare corrosion resistance, corrosion resistance after coating and formability, which comprises: a steel sheet; a first electro-galvanized layer, as a lower layer, in an amount of from 5 to 120 g/m.sup.2 per side, formed on at least one surface of said steel sheet, said first electro-galvanized layer comprising either an electro-galvanized layer consisting essentially of zinc or a compound electro-galvanized layer consisting essentially of zinc, cobalt and at least one of chromium, indium and zirconium; and a second electro-galvanized layer, as an upper layer, in an amount of from 0.2 to 10 g/m.sup.2 per side, formed on said first electro-galvanized layer, said second electro-galvanized layer consisting essentially of an alloy layer of zinc and from 1 to 60 wt. % iron. Said electro-galvanized steel sheet for coating is adapted to serve particularly for external, underside and closed structures of an automobile.
    Type: Grant
    Filed: October 22, 1979
    Date of Patent: February 24, 1981
    Assignee: Nippon Kokan Kabushiki Kaisha
    Inventors: Kazuo Matsudo, Takeshi Adaniya, Masaru Ohmura, Masahiro Shoji, Tsutomu Watanabe
  • Patent number: 4252576
    Abstract: An epitaxial wafer of GaAs.sub.1-x P.sub.x has been doped with nitrogen and used for the production of light emitting diode (LED). The carrier concentration of the conventional GaAs.sub.1-x P.sub.x was from 3.times.10.sup.16 to 2.times.10.sup.17 /cm.sup.3.According to the present invention, the carrier concentration is reduced lower than the conventional concentration and the luminance of LED is increased approximately two or three times the conventional luminance.
    Type: Grant
    Filed: July 6, 1979
    Date of Patent: February 24, 1981
    Assignee: Mitsubishi Monsanto Chemical Co.
    Inventors: Shinichi Hasegawa, Hisanori Fujita
  • Patent number: 4252580
    Abstract: An InP/SiO.sub.2 insulated gate field effect transistor which exhibits power gain at microwave frequencies is manufactured by using an n-type epitaxial semiconducting InP film on a semi-insulating InP substrate and depositing a pyrolytic silicon dioxide insulating film on the conducting InP film to form the gate insulator.
    Type: Grant
    Filed: May 21, 1979
    Date of Patent: February 24, 1981
    Inventor: Louis J. Messick
  • Patent number: 4252581
    Abstract: A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.
    Type: Grant
    Filed: October 1, 1979
    Date of Patent: February 24, 1981
    Assignee: International Business Machines Corporation
    Inventors: Narasipur G. Anantha, Joseph R. Cavaliere, Richard R. Konian, Gurumakonda R. Srinivasan, Herbert I. Stoller, James L. Walsh
  • Patent number: 4252579
    Abstract: A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon.
    Type: Grant
    Filed: May 7, 1979
    Date of Patent: February 24, 1981
    Assignee: International Business Machines Corporation
    Inventors: Irving T. Ho, Jacob Riseman
  • Patent number: 4252582
    Abstract: A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.
    Type: Grant
    Filed: January 25, 1980
    Date of Patent: February 24, 1981
    Assignee: International Business Machines Corporation
    Inventors: Narasipur G. Anantha, Harsaran S. Bhatia, James L. Walsh
  • Patent number: 4251300
    Abstract: A method for forming a shaped buried layer in a semiconductor structure includes the steps of removing a portion of semiconductor material from adjacent the surface of the semiconductor substrate to form an indentation, introducing a dopant into the surface of the indentation to form regions of impurity in the semiconductor substrate, forming a region of epitaxial material on the surface of the indentation, and forming regions of insulating material to surround the epitaxial material.
    Type: Grant
    Filed: May 14, 1979
    Date of Patent: February 17, 1981
    Assignee: Fairchild Camera and Instrument Corporation
    Inventor: Robert E. Caldwell
  • Patent number: 4251599
    Abstract: There is provided an improved plasma spray powder composition for producing bearing surface alloy on a metal substrate, e.g. cast iron, said powder being characterized by the presence therein of a substantial amount of iron, molybdenum and a relatively small amount of silicon. Carbon may also desirably be present in the powder. When plasma sprayed, these powders yield a coating on a metal substrate, e.g. a cast iron piston ring, which is wear and scuff resistant.
    Type: Grant
    Filed: August 23, 1979
    Date of Patent: February 17, 1981
    Assignee: Ramsey Corporation
    Inventor: Harold McCormick
  • Patent number: 4249942
    Abstract: A copper base alloy having improved stress relaxation resistance consisting essentially of about 10.0 to 31% zinc; about 1.0 to 5.0% aluminum; about 0.1 to 3.0% cobalt; about 0.5 to 8% manganese; and the balance essentially copper.
    Type: Grant
    Filed: September 11, 1979
    Date of Patent: February 10, 1981
    Assignee: Olin Corporation
    Inventors: Eugene Shapiro, John M. Vitek, Warren F. Smith, Jr.
  • Patent number: 4249968
    Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.
    Type: Grant
    Filed: December 29, 1978
    Date of Patent: February 10, 1981
    Assignee: International Business Machines Corporation
    Inventors: James R. Gardiner, William A. Pliskin, Martin Revitz, Joseph F. Shepard
  • Patent number: 4247602
    Abstract: Silver alloy wire for the production of jewelry, especially jewelry chains is made of a solder containing nucleus and a jacket of silver or silver alloy wherein the solder containing nucleus has a core of silver or silver alloy surrounded by a layer of brass.
    Type: Grant
    Filed: June 13, 1979
    Date of Patent: January 27, 1981
    Assignee: Ferd. Wagner
    Inventors: Hans Krug, Kurt Heilmann
  • Patent number: 4247326
    Abstract: A free machining steel shape containing bismuth which functions as a liquid metal embrittler. The opportunity for bismuth to function as a liquid metal embrittler is increased by limiting the size of bismuth-containing inclusions to less than five microns.
    Type: Grant
    Filed: August 29, 1979
    Date of Patent: January 27, 1981
    Assignee: Inland Steel Company
    Inventors: Dennis T. Quinto, Debanshu Bhattacharya
  • Patent number: 4246323
    Abstract: An article with an improved MCrAlY coating is disclosed wherein a plasma sprayed MCrAlY coating is provided with a metallic envelope and then hot isostatically pressed to densify the coating and interdiffuse the envelope. Thus, the substrate is provided with a coating which in its bulk is the densified plasma coating with an outer surface zone which is enriched in a metal which enhances the oxidation-corrosion protective properties of the coating. Preferred coatings have a standard CoCrAlY bulk with a metal-enriched surface zone of about 0.02 mm depth. When aluminum is added the surface zone is comprised by weight percent of about 60 Co, 20 Cr and 22 Al. With chromium the surface zone is about 50 Co, 43 Cr and 8.5 Al.
    Type: Grant
    Filed: September 11, 1979
    Date of Patent: January 20, 1981
    Assignee: United Technologies Corporation
    Inventors: Norman S. Bornstein, Francis J. Wallace, Michael A. De Crescente
  • Patent number: 4246322
    Abstract: This invention relates to fabricating wire and particularly wire at least the surface of which consists of platinum or a platinum-based alloy for use in the jewellery industry. The wire according to the invention comprises a first portion at least the outer surface of which consists essentially of platinum or a platinum-based alloy and a second portion in the form of a coating or layer on the outer surface of the first portion, the second portion consisting essentially of a metal or alloy which is soft relative to the platinum or platinum-based alloy. Preferably, the second portion consists essentially of copper.
    Type: Grant
    Filed: February 8, 1979
    Date of Patent: January 20, 1981
    Assignee: Johnson, Matthey & Co., Limited
    Inventors: John E. Wall, Ernest E. Lloyd
  • Patent number: 4243730
    Abstract: A steel sheet having a zinc coating on one side and a uniformly alloyed layer of iron and zinc on the other side, the amount of the alloyed layer being from 0.001 g/m.sup.2 to 1 g/m.sup.2 of zinc and containing from 6 to 20 percent by weight iron.
    Type: Grant
    Filed: April 4, 1979
    Date of Patent: January 6, 1981
    Assignee: Nippon Steel Corporation
    Inventors: Motohiro Nakayama, Kazutsugu Nakajima
  • Patent number: 4242156
    Abstract: A silicon-on-sapphire semiconductor structure, and method of fabricating such structure, in which a silicon nitride layer is provided over the oxide layer. The silicon nitride layer is disposed over the upper edge of the silicon island, and acts to prevent gate oxide breakdown.
    Type: Grant
    Filed: October 15, 1979
    Date of Patent: December 30, 1980
    Assignee: Rockwell International Corporation
    Inventor: John L. Peel
  • Patent number: 4242131
    Abstract: A copper base alloy having improved stress relaxation resistance consisting essentially of: about 15.0 to 31% zinc; about 1.0 to 5.0% aluminum; about 0.1 to less than 1% iron; about 1.1 to 8% manganese; and the balance essentially copper.
    Type: Grant
    Filed: September 11, 1979
    Date of Patent: December 30, 1980
    Assignee: Olin Corporation
    Inventors: Eugene Shapiro, John M. Vitek, Warren F. Smith, Jr.