Patents Examined by Wael M. Fahmy
  • Patent number: 10811527
    Abstract: An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 20, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Abhishek Banerjee, Piet Vanmeerbeek
  • Patent number: 10811450
    Abstract: Image sensors are provided. The image sensors may include a plurality of unit pixels and a color filter array on the plurality of unit pixels. The color filter array may include a color filter unit including four color filters that are arranged in a two-by-two array, and the color filter unit may include two yellow color filters, a cyan color filter, and one of a red color filter or a green color filter.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bomi Kim, BumSuk Kim, Jung-Saeng Kim, Yun Ki Lee, Taesub Jung
  • Patent number: 10804480
    Abstract: Disclosed is a graphene laminate including a first graphene layer, containing an electron-donating functional group, and a second graphene layer, disposed on the first graphene layer and configured to include graphene, wherein the second graphene layer is n-doped with the first graphene layer. Thereby, graphene is doped with amino-group-modified graphene, thus preventing the transparency of graphene from decreasing, and the extent of doping of graphene can be adjusted, and the doping effect can last a long time even without any protective layer.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 13, 2020
    Assignees: CENTER FOR ADVANCED SOFT ELECTRONICS, POSTECH ACADEMY-INDUSTY FOUNDATION
    Inventors: Kilwon Cho, Haena Kim, Boseok Kang
  • Patent number: 10797159
    Abstract: Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lin Wei, Upinder Singh, Raj Verma Purakh
  • Patent number: 10796970
    Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu
  • Patent number: 10790373
    Abstract: A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 29, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yoshiyuki Sakai
  • Patent number: 10790365
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 29, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin Lin, Yu-Hao Ho, Shin-Cheng Lin, Cheng-Tsung Wu
  • Patent number: 10784204
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Wilfred Gomes, Yu Amos Zhang, Ram S. Viswanath, Rajasekaran Swaminathan, Sriram Srinivasan, Yidnekachew S. Mekonnen, Sanka Ganesan, Eduard Roytman, Mathew J. Manusharow
  • Patent number: 10770551
    Abstract: A P-i-N diode structure includes a group III-N semiconductor material disposed on a substrate. An n-doped raised drain structure is disposed on the group III-N semiconductor material. An intrinsic group III-N semiconductor material is disposed on the n-doped raised drain structure. A p-doped group III-N semiconductor material is disposed on the intrinsic group III-N semiconductor material. A first electrode is connected to the p-doped group III-N semiconductor material. A second electrode is electrically coupled to the n-doped raised drain structure. In an embodiment, a group III-N transistor is electrically coupled to the P-i-N diode. In an embodiment, a group III-N transistor is electrically isolated from the P-i-N diode. In an embodiment, a gate electrode and an n-doped raised drain structure are electrically coupled to the n-doped raised drain structure and the second electrode of the P-i-N diode to form the group III-N transistor.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10763194
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS PTE LTD
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Patent number: 10727437
    Abstract: To realize a high-performance liquid crystal display device or light-emitting element using a plastic film. A CPU is formed over a first glass substrate and then, separated from the first substrate. A pixel portion having a light-emitting element is formed over a second glass substrate, and then, separated from the second substrate. The both are bonded to each other. Therefore, high integration can be achieved. Further, in this case, the separated layer including the CPU serves also as a sealing layer of the light-emitting element.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 10700134
    Abstract: This disclosure relates to reduced power consumption OLED displays at reduced cost for reduced information content applications, such as wearable displays. Image quality for wearable displays can be different than for high information content smart phone displays and TVs, where the wearable display has an architecture that in includes, for example, an all phosphorescent device and/or material system that may be fabricated at reduced cost. The reduced power consumption can facilitate wireless and solar charging.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: June 30, 2020
    Assignee: Universal Display Corporation
    Inventors: Michael Hack, Julia J. Brown, Michael Stuart Weaver, Woo-Young So
  • Patent number: 10692991
    Abstract: Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Julien Frougier, Ruilong Xie
  • Patent number: 10692863
    Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 23, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kentaro Nasu, Kenji Nishida
  • Patent number: 10680085
    Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 9, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dominic J. Schepis, Alexander Reznicek, Pranita Kerber, Qiqing C. Ouyang
  • Patent number: 10672824
    Abstract: A pixel unit of an image sensor is provided. The pixel unit includes a semiconductor substrate, a light-sensitive element, a contact and a protection layer. The contact is formed right on the light-sensitive element to enable electrical signals outputted from the light-sensitive element to be transmitted to a peripheral circuit. The protection layer is disposed on the light-sensitive element and surrounds the first contact. The electrical signals of the light-sensitive element can be upward transmitted to the peripheral circuit through the contact. Therefore, the light-sensitive element can occupy a big area, and high quantum efficiency (QE) is achieved accordingly.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Bo-Tsung Tsai
  • Patent number: 10658409
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. U.
    Inventors: Sheng-Chan Li, I-Nan Chen, Tzu-Hsiang Chen, Yu-Jen Wang, Yen-Ting Chiang, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 10658318
    Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei
  • Patent number: 10644005
    Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Deepak Chandra Pandey
  • Patent number: 10644034
    Abstract: An array substrate of display panel comprises a substrate, a first and second transistors disposed on the substrate. The first and second transistors are electrically connected and share a semiconducting layer which comprises a first lateral portion, a turning portion and a bottom portion. The turning portion connects to the first lateral portion. The bottom portion connects to the turning portion. In one embodiment, a first outer edge extending line of the first lateral portion, a second outer edge extending line of the bottom portion and a third outer edge of the turning portion defines a first region. A first inner edge extending line of the first lateral portion, a second inner edge extending line of the bottom portion and a third inner edge of the turning portion defines a second region. The area of the first region is smaller than that of the second region.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 5, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: I-Che Lee, Ying-Tong Lin