Patents Examined by Wael M. Fahmy
  • Patent number: 11158740
    Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Yuan Lu
  • Patent number: 11152439
    Abstract: A transparent display substrate, a transparent display device, and a method of manufacturing a transparent display device, the substrate including a base substrate including a pixel area and a transmission area; a pixel circuit on the pixel area of the base substrate; an insulation layer covering the pixel circuit on the base substrate; a pixel electrode selectively disposed on the pixel area of the base substrate, the pixel electrode being electrically connected to the pixel circuit at least partially through the insulation layer; and a transmitting layer structure selectively disposed on the transmission area of the base substrate, the transmitting layer structure including at least an inorganic material, the inorganic material consisting essentially of silicon oxynitride.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Ho Jung, Chaun-Gi Choi, Young-Sik Yoon, Joo-Hee Jeon, Jung-Yun Jo
  • Patent number: 11145743
    Abstract: A method of forming a comb-shaped transistor device is provided. The method includes forming a stack of alternating sacrificial spacer segments and channel segments on a substrate. The method further includes forming channel sidewalls on opposite sides of the stack of alternating sacrificial spacer segments and channel segments, and dividing the stack of alternating sacrificial spacer segments and channel segments into alternating sacrificial spacer slabs and channel slabs, wherein the channel slabs and channel sidewalls form a pair of comb-like structures. The method further includes trimming the sacrificial spacer slabs and channel slabs to form a nanosheet column of sacrificial plates and channel plates, and forming source/drains on opposite sides of the sacrificial plates and channel plates.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 11145747
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure protruding therefrom, an insulating layer is over the substrate to cover the fin structure, a gate structure in the insulating layer and over the fin structure, and source and drain features covered by the insulating layer and over the fin structure on opposing sidewall surfaces of the gate structure. The gate structure includes a gate electrode layer, a conductive sealing layer covering the gate electrode layer, and a gate dielectric layer between the fin structure and the gate electrode layer and surrounding the gate electrode layer and the conductive sealing layer. The gate electrode layer has a material removal rate that is higher than the material removal rate of the conductive sealing layer in a chemical mechanical polishing process.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yun Hsu, Hsiao-Kuan Wei
  • Patent number: 11121207
    Abstract: A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Abbas Ali, Sopa Chevacharoenkul, Jarvis Benjamin Jacobs
  • Patent number: 11049828
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices manufactured thereby, that comprise utilizing a compressed interconnection structure (e.g., a compressed solder ball, etc.) in an encapsulating process to form an aperture in an encapsulant. The compressed interconnection structure may then be reformed in the aperture.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: June 29, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Gyu Wan Han, Jin Seong Kim, Byong Woo Cho
  • Patent number: 11011524
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11005037
    Abstract: A method of manufacturing an integrated circuit device. In the method, a plurality of contacts are formed over a substrate, and one or more bottom electrode layers are formed over the plurality of contacts. A first dielectric layer is formed such that a first base region of the first dielectric layer is in contact with the one or more bottom electrode layers and a second base region of the first dielectric layer is not in contact with the one or more bottom electrode layers. One or more top electrode layers are formed over the first dielectric layer. Patterning is then performed by etching through the one or more top electrode layers and by etching through the first dielectric layer to form a metal-insulator-metal structure. The patterning removes a portion of the second base region, but does not remove the first base region.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10991642
    Abstract: An IC includes a bare die and a multiplexed pin. The multiplexed pin is electrically connected to first and second switch circuits, the first and second switch circuits are respectively connected to first and second circuit modules disposed on the bare die and control a connection between the first and second circuit modules and the multiplexed pin, the first switch circuit is connected to a first die pad by a metal layer trace within the bare die, the second switch circuit is connected to a second die pad by a metal layer trace within the bare die, and the first and second die pads are connected to the multiplexed pin through a bond wire respectively. The bare die with a larger number of die pads can be packaged into an IC package with a smaller number of chip pins.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: April 27, 2021
    Assignee: JOHNSON ELECTRIC INTERNATIONAL AG
    Inventors: Chiping Sun, Shinghin Yeung, Haibo Jiang, Qiubao Wang, Enhui Wang
  • Patent number: 10978568
    Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Mark R. Brazier, Anand S. Murthy, Tahir Ghani, Owen Y. Loh
  • Patent number: 10971427
    Abstract: Thermal coupling with between an electrical component, such as a CPU, and a heatsink can be provided by a movable heatsink insert separate from the heatsink. This movable heatsink insert can be placed on the electrical component. The heatsink can be thermally coupled to that additional thermal conductor. The heatsink, which is attached to the printed circuit board, is not in direct contact with the electrical component, reducing the likelihood that the heatsink could cause bending of the printed circuit board by pressing down on the electrical component. Further, a spring coupled between the heatsink and the movable heatsink insert can provide further pressure relief such that the heatsink assembly can be attached to an electrical component without applying excessive force to the electrical component.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: April 6, 2021
    Assignee: Dell Products L.P.
    Inventors: Qinghong He, Edward Davis Geist
  • Patent number: 10971685
    Abstract: A selective device includes a first electrode, a second electrode, a switch device, and a non-linear resistive device. The second electrode is disposed to face the first electrode. The switch device is provided between the first electrode and the second electrode. The non-linear resistive device contains one or more of boron (B), silicon (Si), and carbon (C). The non-linear resistive device is coupled to the switch device in series.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: April 6, 2021
    Assignee: SONY CORPORATION
    Inventors: Kazuhiro Ohba, Minoru Ikarashi
  • Patent number: 10950548
    Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuichi Sano, Atsushi Kurokawa, Kazuya Kobayashi
  • Patent number: 10943940
    Abstract: Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Chuang Wu, Jhy-Jyi Sze, Yu-Jen Wang, Yen-Chang Chu, Shyh-Fann Ting, Ching-Chun Wang
  • Patent number: 10923493
    Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Albert Fayrushin, Haitao Liu, Mojtaba Asadirad
  • Patent number: 10916557
    Abstract: According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shunpei Takeshita, Namiki Yoshikawa, Kazuhide Takamura, Naoki Yamamoto
  • Patent number: 10916581
    Abstract: A multilayered magnetic free layer structure is provided that includes a first magnetic free layer and a second magnetic free layer separated by a non-magnetic layer in which the first magnetic free layer is composed of an ordered magnetic alloy. The ordered magnetic alloy provides a first magnetic free layer that has low moment, but is strongly magnetic. The use of such an ordered magnetic alloy first magnetic free layer in a multilayered magnetic free layer structure substantially reduces the switching current needed to reorient the magnetization of the two magnetic free layers.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Daniel Worledge, Guohan Hu
  • Patent number: 10910324
    Abstract: A semiconductor device has a configuration in which a stacked assembly and a resin case are combined. The stacked assembly includes a semiconductor element, a stacked substrate on which the semiconductor element is mounted, and a metal substrate on which the stacked substrate is mounted. In the resin case, a notch groove is provided at a corner portion for reducing a stress. At least one of a width and a length of the notch groove is 2 mm or more.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 2, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tatsuhiko Asai, Katsumi Taniguchi
  • Patent number: 10903181
    Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 26, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Boo Yang Jung, Jong Sik Paek, Choon Heung Lee, In Bae Park, Sang Won Kim, Sung Kyu Kim, Sang Gyu Lee
  • Patent number: 10896963
    Abstract: Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Tahir Ghani, Szuya S. Liao