Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

Abstract: A P-i-N diode structure includes a group III-N semiconductor material disposed on a substrate. An n-doped raised drain structure is disposed on the group III-N semiconductor material. An intrinsic group III-N semiconductor material is disposed on the n-doped raised drain structure. A p-doped group III-N semiconductor material is disposed on the intrinsic group III-N semiconductor material. A first electrode is connected to the p-doped group III-N semiconductor material. A second electrode is electrically coupled to the n-doped raised drain structure. In an embodiment, a group III-N transistor is electrically coupled to the P-i-N diode. In an embodiment, a group III-N transistor is electrically isolated from the P-i-N diode. In an embodiment, a gate electrode and an n-doped raised drain structure are electrically coupled to the n-doped raised drain structure and the second electrode of the P-i-N diode to form the group III-N transistor.

Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.

Abstract: To realize a high-performance liquid crystal display device or light-emitting element using a plastic film. A CPU is formed over a first glass substrate and then, separated from the first substrate. A pixel portion having a light-emitting element is formed over a second glass substrate, and then, separated from the second substrate. The both are bonded to each other. Therefore, high integration can be achieved. Further, in this case, the separated layer including the CPU serves also as a sealing layer of the light-emitting element.

Abstract: This disclosure relates to reduced power consumption OLED displays at reduced cost for reduced information content applications, such as wearable displays. Image quality for wearable displays can be different than for high information content smart phone displays and TVs, where the wearable display has an architecture that in includes, for example, an all phosphorescent device and/or material system that may be fabricated at reduced cost. The reduced power consumption can facilitate wireless and solar charging.

Abstract: A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

Abstract: Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

Abstract: A pixel unit of an image sensor is provided. The pixel unit includes a semiconductor substrate, a light-sensitive element, a contact and a protection layer. The contact is formed right on the light-sensitive element to enable electrical signals outputted from the light-sensitive element to be transmitted to a peripheral circuit. The protection layer is disposed on the light-sensitive element and surrounds the first contact. The electrical signals of the light-sensitive element can be upward transmitted to the peripheral circuit through the contact. Therefore, the light-sensitive element can occupy a big area, and high quantum efficiency (QE) is achieved accordingly.

Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.

Abstract: An array substrate of display panel comprises a substrate, a first and second transistors disposed on the substrate. The first and second transistors are electrically connected and share a semiconducting layer which comprises a first lateral portion, a turning portion and a bottom portion. The turning portion connects to the first lateral portion. The bottom portion connects to the turning portion. In one embodiment, a first outer edge extending line of the first lateral portion, a second outer edge extending line of the bottom portion and a third outer edge of the turning portion defines a first region. A first inner edge extending line of the first lateral portion, a second inner edge extending line of the bottom portion and a third inner edge of the turning portion defines a second region. The area of the first region is smaller than that of the second region.

Abstract: A semiconductor device includes a substrate, an electronic component, a ring structure and an adhesive layer. The substrate has a first surface. The electronic component is over the first surface of the substrate. The ring structure is over the first surface of the substrate, wherein the ring structure includes a first part having a first height, and a second part recessed from the bottom surface and having a second height lower than the first height. The adhesive layer is interposed between the first part of the ring structure and the substrate, and between the second part of the ring structure and the substrate.

Abstract: A semiconductor package device includes a carrier, an electronic component, a package body and an antenna. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The electronic component is disposed on the first surface of the carrier. The package body is disposed on the first surface of the carrier and encapsulates the electronic component. The antenna is disposed on at least a portion of the lateral surface of the carrier.

Abstract: A semiconductor device includes a substrate structure. The Substrate structure includes a substrate, a plurality of fins each protruding from the substrate structure, a germanium layer on a top surface of the fins, spacers on opposite sides of the germanium layer, an oxide layer on a surface of the germanium layer between the spacers, the oxide layer comprising silicon and germanium, a high-k dielectric layer on the oxide layer and on inner sidewalls of the spacers, and a gate electrode on the high-k dielectric layer.

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

Abstract: A semiconductor device includes a semiconductor substrate in which a through hole is formed, a first wiring that is provided on a first surface of the semiconductor substrate, an insulating layer provided on an inner surface of the through hole and a second surface of the semiconductor substrate, and a second wiring that is provided on a surface of the insulating layer and electrically connected to the first wiring in an opening. The surface of the insulating layer includes a first region, a second region, a third region, a fourth region that is curved to continuously connect the first and the second regions, and a fifth region that is curved to continuously connect the second and the third regions. An average inclination angle of the second region is smaller than that of the first region and is smaller than that of the inner surface.

Abstract: An image sensor is provided. The image sensor includes a visible light receiving portion and an infrared receiving portion. The visible light receiving portion is configured to receive a visible light. The infrared receiving portion is configured to receive infrared. The visible light receiving portion includes a color filter ball layer configured to collect the visible light. In some embodiments of the present invention, the infrared receiving portion includes an infrared pass filter ball layer configured to collect the infrared. In some other embodiments of the present invention, the infrared receiving portion includes a white filter ball layer configured to collect the infrared.

Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.