Patents Examined by Wael M. Fahmy
  • Patent number: 10490442
    Abstract: An example embodiment may include a method for blocking one or more portions of one or more trenches during manufacture of a semiconductor structure. The method may include (i) providing a substrate comprising one or more trenches, and a dielectric material under the one or more trenches, (ii) providing a first overlayer on the substrate, thereby filling the one or more trenches, the first overlayer having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide, (iii) covering a first area of the top surface, situated directly above the one or more portions and corresponding thereto, with a block pattern of the condensed photo-condensable metal oxide, thereby leaving a second area of the top surface, having at least another portion of at least one of the trenches thereunder, uncovered.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 26, 2019
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Ming Mao, Peter De Schepper, Michael Kocsis
  • Patent number: 10490356
    Abstract: A capacitor includes a body including a substrate and a capacitance layer disposed on the substrate. The substrate includes a plurality of first trenches penetrating from one surface of the substrate to an interior of the substrate, and a first capacitor layer disposed on the one surface of the substrate and in the first trenches. The first capacitor layer includes a first dielectric layer and first and second electrodes disposed on opposing sides thereof. The capacitance layer includes a plurality of second trenches penetrating from one surface of the capacitance layer to an interior of the capacitance layer, and a second capacitor layer disposed on the one surface of the capacitance layer and in the second trenches. The second capacitor layer includes a second dielectric layer and third and fourth electrodes disposed on opposing sides thereof. A method of manufacturing the capacitor is also provided.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong Hoon Ryou, Dong Sik Yoo, Seung Hun Han, No Il Park, Seung Mo Lim, Hyun Ho Shin
  • Patent number: 10483350
    Abstract: There is provided a semiconductor device, including: a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode electrically connec
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: November 19, 2019
    Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tohru Nakamura, Tomoyoshi Mishima, Hiroshi Ohta, Yasuhiro Yamamoto, Fumimasa Horikiri
  • Patent number: 10475782
    Abstract: Provided are an ESD protection diode and an electronic device including the same. An ESD protection diode and an electronic device including the same according to an embodiment of the inventive concept include first to fifth wells. The first well is connected to a first voltage terminal. The second well is connected to a second voltage terminal. The third well is connected to the input/output terminal. The fourth well is disposed between the first well and the third well, and the fifth well is disposed between the second well and the third well. The first to third wells are N-type wells, and the fourth and fifth wells are P-type wells. The first well includes a first N+ diffusion region and the second well includes a second N+ diffusion region. The fourth well includes a first P+ diffusion region and the fifth well includes a second P+ diffusion region.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: November 12, 2019
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, DANKOOK UNIVERSITY
    Inventors: Jimin Oh, Yong-Seo Koo, Yil Suk Yang, Jongdae Kim
  • Patent number: 10468487
    Abstract: A semiconductor device in which an interlayer insulation film covers striped gate electrodes with a thickness larger than a thickness of a gate oxide film. The interlayer insulation film includes first contact holes outside each striped trench, and second contact holes inside the striped trench. In a plan view, striped active regions and striped contact regions both extending in a longitudinal direction exist. The striped active regions and the striped contact regions are alternately and repeatedly disposed in a direction perpendicular to the longitudinal direction. In each of the striped active regions, the source electrode is connected to a source region through the first contact hole. In each of the striped contact regions, the source electrode is connected to a protective diffusion layer through the second contact hole.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: November 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsutoshi Sugawara, Rina Tanaka, Yutaka Fukui, Kohei Adachi, Kazuya Konishi
  • Patent number: 10461066
    Abstract: An optical package containing optical sensor/detector pairs co-housed with a non-optical sensor and processes for fabricating the optical package are described herein. Traditional package structures require the use of clear mold compounds to protect the sensitive dies, but such compounds degrade with time and temperature. The optical package described herein uses a special glass top cover that is transparent in the entire electro-magnetic spectral region required by the contained dies.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: October 29, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kumar Nagarajan, Seshasayee S. Ankireddi
  • Patent number: 10439008
    Abstract: The present application discloses an organic light-emitting display panel and a manufacturing method thereof, and an organic light-emitting display device. The organic light-emitting display panel comprises a substrate, a first electrode layer, a second electrode layer, an organic light-emitting functional layer formed between the first electrode layer and the second electrode layer and comprising a plurality of first optical adjustment units, a plurality of second optical adjustment units and at least one light emitting layer covering a display area of the organic light-emitting display panel, and a pixel definition layer partitioning the organic light-emitting functional layer to form a pixel array comprising a first color pixel, a second color pixel and a third color pixel in an array arrangement.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 8, 2019
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Shuang Cheng, Xiangcheng Wang, Jinghua Niu, Hamada Yuji, Jianyun Wang
  • Patent number: 10431490
    Abstract: A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 1, 2019
    Assignee: Akoustis, Inc.
    Inventor: Jeffrey B. Shealy
  • Patent number: 10427933
    Abstract: A MEMS device is provided with: a supporting base, having a bottom surface in contact with an external environment; a sensor die, which is of semiconductor material and integrates a micromechanical detection structure; a sensor frame, which is arranged around the sensor die and is mechanically coupled to a top surface of the supporting base; and a cap, which is arranged above the sensor die and is mechanically coupled to a top surface of the sensor frame, a top surface of the cap being in contact with an external environment. The sensor die is mechanically decoupled from the sensor frame.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 1, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enri Duqi, Sebastiano Conti
  • Patent number: 10411139
    Abstract: Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.
    Type: Grant
    Filed: July 22, 2017
    Date of Patent: September 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tomohiro Yamashita
  • Patent number: 10403734
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haigou Huang
  • Patent number: 10403742
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Patent number: 10396037
    Abstract: There is provided a fan-out semiconductor device in which a first package having a semiconductor chip disposed therein and having a fan-out form and a second package having a passive component disposed therein and having a fan-out form are stacked in a vertical direction so that the semiconductor chip and the passive component are electrically connected to each other by a path as short as possible.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jun Oh Hwang, Kwang Yun Kim, Ki Jung Sung
  • Patent number: 10384930
    Abstract: Systems and methods are provided that provide a getter in a micromechanical system. In some embodiments, a microelectromechanical system (MEMS) is bonded to a substrate. The MEMS and the substrate have a first cavity and a second cavity therebetween. A first getter is provided on the substrate in the first cavity and integrated with an electrode. A second getter is provided in the first cavity over a passivation layer on the substrate. In some embodiments, the first cavity is a gyroscope cavity, and the second cavity is an accelerometer cavity.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: August 20, 2019
    Assignee: INVENSENSE, INC.
    Inventors: Daesung Lee, Jeff Chunchieh Huang, Jongwoo Shin, Bongsang Kim, Logeeswaran Veerayah Jayaraman
  • Patent number: 10388713
    Abstract: An organic light emitting display device includes a display panel including a display region where a plurality of pixels are disposed, a pad region including a bending region and a pad electrode region where pad electrodes are disposed, a polarizing layer disposed in the display region, and a lower protection film disposed on a lower surface of the display panel. The lower protection film includes a first and a second lower protection film pattern. The first lower protection film pattern is disposed in the display region, and the second lower protection film pattern in the pad electrode region such that a lower surface of the display panel in the bending region is exposed. The bending protection layer has an upper surface with a height that is less than a height of the polarizing layer, and is disposed in the bending region on the display panel.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Euncheol Son, Dongbin Um, Kichang Lee, Myoung-Ha Jeon, Sangkyu Choi
  • Patent number: 10388593
    Abstract: A sensor is disclosed. The sensor comprises a first substrate; a second substrate positioned relative to the first substrate; a first electrode located between the first substrate and the second substrate, the first electrode formed on the second substrate; a sensing portion covering at least a part of the first electrode and further covering at least a portion of the second substrate; a pad electrode located between the first substrate and the second substrate, wherein the pad electrode is formed on the second substrate and is electrically coupled to the first electrode; and a bonding pad located between the first substrate and the second substrate, wherein the bonding pad is formed on the first substrate and is electrically coupled to the pad electrode.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: August 20, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Insung Hwang, Wonhyeog Jin, Moosub Kim, Yunguk Jang
  • Patent number: 10373999
    Abstract: An image sensor is disclosed. The image sensor includes: a common node heavily doped with dopants of a first conductivity type, the common node being within the substrate and abutting the front surface of the substrate; and a sensing node heavily doped with dopants of a second conductivity type opposite to the first conductivity type, the sensing node being within the substrate and abutting the front surface of the substrate; an interconnect structure, wherein the front surface of the substrate faces the interconnect structure; a distributed Bragg reflector (DBR) between the front surface of the substrate and the interconnect structure; a first contact plug passing through the DBR and coupling the common node to the interconnect structure; and a second contact plug passing through the DBR and coupling the sensing node to the interconnect structure.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yuichiro Yamashita
  • Patent number: 10365244
    Abstract: An ion-sensitive structure includes a semiconductor structure and a layer stack disposed on the semiconductor structure having a doped intermediate layer including a doping material and a first metal oxide material. The semiconductor structure is configured to change an electric characteristic based on a contact of the ion-sensitive structure with an electrolyte including ions.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: July 30, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Eberhard Kurth, Christian Kunath, Harald Schenk
  • Patent number: 10347710
    Abstract: A method for forming a thin film resistor (TFR) without via penetration and the resulting device are provided. Embodiments include forming a first ILD over a substrate; forming a second ILD over the first ILD; forming a first metal layer in the second ILD; forming a first nitride layer over the second ILD and the first metal layer; forming a third ILD over the first nitride layer; forming vias through the third ILD and the first nitride layer, coupled to the first metal layer; forming a TFR layer over two of the vias and the third ILD between the two vias; forming a second nitride layer over the TFR layer and the third ILD; forming a fourth ILD over the second nitride layer; and forming a second metal layer in the fourth ILD and the second nitride layer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Purakh Raj Verma, Kemao Lin
  • Patent number: 10340253
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsualnt. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih