Patents Examined by Wael M. Fahmy
  • Patent number: 10886227
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-Jin Kim, Chang-Hwa Kim, Hwi-Chan Jun, Chui-Hong Park, Jae-Seok Yang, Kwan-Young Chun
  • Patent number: 10879455
    Abstract: Methods of fabricating MRAM devices are provided. The method includes forming an etch stop layer over a substrate, and depositing a bottom electrode layer on the etch stop layer. The method also includes patterning the bottom electrode layer to form a bottom electrode. The method further includes depositing a magnetic tunnel junction (MTJ) layer on the bottom electrode, and depositing a top electrode layer on the MTJ layer. In addition, the method includes patterning the top electrode layer to form a top electrode, and patterning the MTJ layer to form an MTJ structure.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 10879241
    Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 29, 2020
    Assignee: INTEL Corporation
    Inventors: Glenn A. Glass, Prashant Majhi, Anand S. Murthy, Tahir Ghani, Daniel B. Aubertine, Heidi M. Meyer, Karthik Jambunathan, Gopinath Bhimarasetti
  • Patent number: 10872776
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer. A gate dielectric layer of the gate stack adjoins the first layer and the second layer.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz
  • Patent number: 10840235
    Abstract: Provided is a semiconductor device with a reduced variation in temperature among a plurality of unit transistors. A semiconductor device includes: a semiconductor substrate; and a transistor group including at least one column in which a plurality of unit transistors are aligned and arranged along a first axis on the semiconductor substrate. A first column of the at least one column includes: a first group of transistors including two of the unit transistors that are adjacent to each other with a first distance therebetween, and a second group of transistors including two of the unit transistors that are adjacent to each other with a second distance therebetween, the first group of transistors is disposed at a position closer to a center of the first column along the first axis than the second group of transistors, and the first distance is larger than the second distance.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yuri Honda, Fumio Harima, Kazuhito Nakai
  • Patent number: 10833101
    Abstract: A vertically alternating sequence of multi-fingered silicon-germanium layers and multi-fingered silicon layers is formed over a substrate. The multi-fingered silicon-germanium layers include silicon-germanium wires, and the multi-fingered silicon layers include silicon wires. Tubular memory films and multi-fingered gate electrodes are formed. Each gate electrode includes a respective gate electrode bar which overlies the silicon wires and a respective set of vertically-extending gate electrode fingers which is adjoined to a bottom portion of the respective gate electrode bar and spaced apart by the silicon wires. The multi-fingered silicon-germanium layers are removed selective to multi-fingered silicon layers. First active regions are formed at an end portion of each of the silicon wires. Second active regions are formed on silicon plate portions of the multi-fingered silicon layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 10, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shigeki Shimomura, Satoru Mayuzumi, Hiroyuki Ogawa
  • Patent number: 10825962
    Abstract: A light emitting device can include a light emitting structure including a p-GaN based semiconductor layer, an active layer having multiple quantum wells, and an n-GaN based semiconductor layer; a p-electrode and an n-electrode electrically connecting with the light emitting structure, respectively, wherein the n-electrode has a plurality of layers; a first passivation layer including a first portion contacting a portion of the n-electrode, a second portion vertically overlapped with the p-electrode, and a third portion that extends outside of outermost side surfaces of the light emitting structure; a phosphor layer disposed on a top surface of the light emitting structure; and a second passivation layer including a first portion disposed between the phosphor layer and the top surface of the light emitting structure, and a second portion disposed on the outermost side surfaces of the light emitting structure, in which the phosphor layer includes a pattern to bond a wire with a p-pad on a portion of the p-elec
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 3, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Myung Cheol Yoo
  • Patent number: 10811450
    Abstract: Image sensors are provided. The image sensors may include a plurality of unit pixels and a color filter array on the plurality of unit pixels. The color filter array may include a color filter unit including four color filters that are arranged in a two-by-two array, and the color filter unit may include two yellow color filters, a cyan color filter, and one of a red color filter or a green color filter.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bomi Kim, BumSuk Kim, Jung-Saeng Kim, Yun Ki Lee, Taesub Jung
  • Patent number: 10811527
    Abstract: An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 20, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Abhishek Banerjee, Piet Vanmeerbeek
  • Patent number: 10804480
    Abstract: Disclosed is a graphene laminate including a first graphene layer, containing an electron-donating functional group, and a second graphene layer, disposed on the first graphene layer and configured to include graphene, wherein the second graphene layer is n-doped with the first graphene layer. Thereby, graphene is doped with amino-group-modified graphene, thus preventing the transparency of graphene from decreasing, and the extent of doping of graphene can be adjusted, and the doping effect can last a long time even without any protective layer.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 13, 2020
    Assignees: CENTER FOR ADVANCED SOFT ELECTRONICS, POSTECH ACADEMY-INDUSTY FOUNDATION
    Inventors: Kilwon Cho, Haena Kim, Boseok Kang
  • Patent number: 10797159
    Abstract: Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lin Wei, Upinder Singh, Raj Verma Purakh
  • Patent number: 10796970
    Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu
  • Patent number: 10790365
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 29, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin Lin, Yu-Hao Ho, Shin-Cheng Lin, Cheng-Tsung Wu
  • Patent number: 10790373
    Abstract: A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 29, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yoshiyuki Sakai
  • Patent number: 10784204
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Wilfred Gomes, Yu Amos Zhang, Ram S. Viswanath, Rajasekaran Swaminathan, Sriram Srinivasan, Yidnekachew S. Mekonnen, Sanka Ganesan, Eduard Roytman, Mathew J. Manusharow
  • Patent number: 10770551
    Abstract: A P-i-N diode structure includes a group III-N semiconductor material disposed on a substrate. An n-doped raised drain structure is disposed on the group III-N semiconductor material. An intrinsic group III-N semiconductor material is disposed on the n-doped raised drain structure. A p-doped group III-N semiconductor material is disposed on the intrinsic group III-N semiconductor material. A first electrode is connected to the p-doped group III-N semiconductor material. A second electrode is electrically coupled to the n-doped raised drain structure. In an embodiment, a group III-N transistor is electrically coupled to the P-i-N diode. In an embodiment, a group III-N transistor is electrically isolated from the P-i-N diode. In an embodiment, a gate electrode and an n-doped raised drain structure are electrically coupled to the n-doped raised drain structure and the second electrode of the P-i-N diode to form the group III-N transistor.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10763194
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS PTE LTD
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Patent number: 10727437
    Abstract: To realize a high-performance liquid crystal display device or light-emitting element using a plastic film. A CPU is formed over a first glass substrate and then, separated from the first substrate. A pixel portion having a light-emitting element is formed over a second glass substrate, and then, separated from the second substrate. The both are bonded to each other. Therefore, high integration can be achieved. Further, in this case, the separated layer including the CPU serves also as a sealing layer of the light-emitting element.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 10700134
    Abstract: This disclosure relates to reduced power consumption OLED displays at reduced cost for reduced information content applications, such as wearable displays. Image quality for wearable displays can be different than for high information content smart phone displays and TVs, where the wearable display has an architecture that in includes, for example, an all phosphorescent device and/or material system that may be fabricated at reduced cost. The reduced power consumption can facilitate wireless and solar charging.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: June 30, 2020
    Assignee: Universal Display Corporation
    Inventors: Michael Hack, Julia J. Brown, Michael Stuart Weaver, Woo-Young So
  • Patent number: 10692991
    Abstract: Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Julien Frougier, Ruilong Xie