Patents Examined by Wael M. Fahmy
  • Patent number: 10658318
    Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei
  • Patent number: 10644034
    Abstract: An array substrate of display panel comprises a substrate, a first and second transistors disposed on the substrate. The first and second transistors are electrically connected and share a semiconducting layer which comprises a first lateral portion, a turning portion and a bottom portion. The turning portion connects to the first lateral portion. The bottom portion connects to the turning portion. In one embodiment, a first outer edge extending line of the first lateral portion, a second outer edge extending line of the bottom portion and a third outer edge of the turning portion defines a first region. A first inner edge extending line of the first lateral portion, a second inner edge extending line of the bottom portion and a third inner edge of the turning portion defines a second region. The area of the first region is smaller than that of the second region.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 5, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: I-Che Lee, Ying-Tong Lin
  • Patent number: 10644005
    Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Deepak Chandra Pandey
  • Patent number: 10629545
    Abstract: A semiconductor device includes a substrate, an electronic component, a ring structure and an adhesive layer. The substrate has a first surface. The electronic component is over the first surface of the substrate. The ring structure is over the first surface of the substrate, wherein the ring structure includes a first part having a first height, and a second part recessed from the bottom surface and having a second height lower than the first height. The adhesive layer is interposed between the first part of the ring structure and the substrate, and between the second part of the ring structure and the substrate.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Pai-Yuan Li, Shu-Chia Hsu, Hsiang-Fan Lee, Szu-Po Huang
  • Patent number: 10622318
    Abstract: A semiconductor package device includes a carrier, an electronic component, a package body and an antenna. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The electronic component is disposed on the first surface of the carrier. The package body is disposed on the first surface of the carrier and encapsulates the electronic component. The antenna is disposed on at least a portion of the lateral surface of the carrier.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 14, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Seokbong Kim, Sunju Park
  • Patent number: 10615268
    Abstract: A semiconductor device includes a substrate structure. The Substrate structure includes a substrate, a plurality of fins each protruding from the substrate structure, a germanium layer on a top surface of the fins, spacers on opposite sides of the germanium layer, an oxide layer on a surface of the germanium layer between the spacers, the oxide layer comprising silicon and germanium, a high-k dielectric layer on the oxide layer and on inner sidewalls of the spacers, and a gate electrode on the high-k dielectric layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: April 7, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10615220
    Abstract: A semiconductor device includes a semiconductor substrate in which a through hole is formed, a first wiring that is provided on a first surface of the semiconductor substrate, an insulating layer provided on an inner surface of the through hole and a second surface of the semiconductor substrate, and a second wiring that is provided on a surface of the insulating layer and electrically connected to the first wiring in an opening. The surface of the insulating layer includes a first region, a second region, a third region, a fourth region that is curved to continuously connect the first and the second regions, and a fifth region that is curved to continuously connect the second and the third regions. An average inclination angle of the second region is smaller than that of the first region and is smaller than that of the inner surface.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: April 7, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Noburo Hosokawa, Nao Inoue, Katsumi Shibayama
  • Patent number: 10615128
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Patent number: 10600788
    Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
  • Patent number: 10600833
    Abstract: An image sensor is provided. The image sensor includes a visible light receiving portion and an infrared receiving portion. The visible light receiving portion is configured to receive a visible light. The infrared receiving portion is configured to receive infrared. The visible light receiving portion includes a color filter ball layer configured to collect the visible light. In some embodiments of the present invention, the infrared receiving portion includes an infrared pass filter ball layer configured to collect the infrared. In some other embodiments of the present invention, the infrared receiving portion includes a white filter ball layer configured to collect the infrared.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 24, 2020
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yu-Jui Hsieh, Po-Nan Chen
  • Patent number: 10593789
    Abstract: A semiconductor apparatus includes a semiconductor substrate including a semiconductor device. The semiconductor device includes a first n-type buffer layer, a second n-type buffer layer, and a first p-type semiconductor region. A first maximum peak concentration of first n-type carriers contained in the first n-type buffer layer is smaller than a second maximum peak concentration of second n-type carriers contained in the second n-type buffer layer. The first p-type semiconductor region is formed in the first n-type buffer layer. The first p-type semiconductor region has a narrower width than the first n-type buffer layer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 17, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Suzuki, Mitsuru Kaneda, Koichi Nishi
  • Patent number: 10580753
    Abstract: According to an embodiment of a method of manufacturing a plurality of semiconductor devices on a wafer, the method includes forming a structure layer comprising a plurality of same semiconductor device structures and providing a protective layer on the structure layer. The protective layer on a first one of the plurality of semiconductor device structures differs from the protective layer on a second one of the plurality of semiconductor device structures.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Martin Mischitz, Harald Huber, Michael Knabl, Claudia Sgiarovello, Caterina Travan, Andrew Wood
  • Patent number: 10566266
    Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Heat Bit Park, Ji Hwan Kim, Dong Uk Lee
  • Patent number: 10566362
    Abstract: A method for forming an image sensor includes: providing a first device including a visible light receiving portion and an infrared receiving portion; coating a first infrared cutoff filter on the first device; patterning plural photoresists on the first infrared cutoff filter located in the visible light receiving portion to form a second device; etching the second device until a first filter of the first device is exposed to form an infrared cutoff filter and an infrared cutoff filter grid located in the visible light receiving portion, in which the infrared cutoff filter grid is located on the infrared cutoff filter; filling a color filter in the infrared cutoff filter grid and forming a second filter on the first filter; and disposing a spacer layer and a micro-lens layer on the color filter and the second filter sequentially.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: February 18, 2020
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yu-Jui Hsieh, Po-Nan Chen
  • Patent number: 10541332
    Abstract: A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 21, 2020
    Assignee: Sony Corporation
    Inventor: Yuki Miyanami
  • Patent number: 10504869
    Abstract: To improve a performance of a semiconductor device, a semiconductor device includes a lead electrically coupled to a semiconductor chip via a wire. An inner portion of the lead, the semiconductor chip, and the wire are sealed by a sealing body (a resin sealing body). The wire is bonded to an upper surface of a wire bonding portion of the inner portion of the lead. A metal film is formed on a lower surface of the inner portion of the lead, which is on an opposite side to the upper surface. No metal film is formed on the upper surface of the wire bonding portion.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: December 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Yasushi Takahashi
  • Patent number: 10505054
    Abstract: High speed optoelectronic devices and associated methods are provided. In one aspect, for example, a high speed optoelectronic device can include a silicon material having an incident light surface, a first doped region and a second doped region forming a semiconductive junction in the silicon material, and a textured region coupled to the silicon material and positioned to interact with electromagnetic radiation. The optoelectronic device has a response time of from about 1 picosecond to about 5 nanoseconds and a responsivity of greater than or equal to about 0.4 A/W for electromagnetic radiation having at least one wavelength from about 800 nm to about 1200 nm.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: December 10, 2019
    Assignee: SiOnyx, LLC
    Inventors: James E. Carey, Drake Miller
  • Patent number: 10497857
    Abstract: A semiconductor device may include a bottom electrode contact and a magnetic tunnel junction on the bottom electrode contact. The semiconductor device may include a capping insulating layer covering side surfaces of the magnetic tunnel junction. A thickness of the capping insulating layer may be larger than a vertical height of the magnetic tunnel junction. The bottom electrode contact may be in a mold insulating layer on a substrate. The semiconductor device may include a top electrode on the magnetic tunnel junction. The bottom electrode contact may include a monometallic material. The top electrode may include a conductive metal nitride. The semiconductor device may be configured to improve the measurement sensitivity of a semiconductor inspection system with regard to perpendicular magnetization characteristics of magnetic layers included in the magnetic tunnel junction.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eunsun Noh
  • Patent number: 10496134
    Abstract: A display device includes a curved plastic substrate, a display element layer over a first surface of the plastic substrate, a thin film encapsulation layer over the display element layer, a light absorption layer curved in conformity with the plastic substrate, the light absorption layer being over a second surface of the plastic substrate, the second surface being opposite to the first surface, a cushion layer over a fourth surface of the light absorption layer, a third surface of the light absorption layer facing the plastic substrate, and the fourth surface of the light absorption layer being opposite the third surface, and an electrostatic shielding layer over the cushion layer, at least one of the cushion layer and the electrostatic shielding layer has a cut pattern in a thickness direction thereof.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaechun Park, Woosong Kim, Kyujin Cho
  • Patent number: 10497776
    Abstract: The present disclosure relates to a method of etching a narrow gap using one or more parallel releasing structures to improve etching performance, and an associated apparatus. In some embodiments, the method provides a semiconductor substrate with a narrow gap having a sacrificial material. One or more parallel releasing structures are formed within the semiconductor substrate at positions that abut the narrow gap. An etching process is then performed to simultaneously remove the sacrificial material from the narrow gap along a first direction from the one or more parallel releasing structures and along a second direction, perpendicular to the first direction. By simultaneously etching the sacrificial material from both the direction of the narrow gap and from the direction of the one or more parallel releasing structures, the sacrificial material is removed in less time, since the etch is not limited by a size of the narrow gap.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Te-Hao Lee