Abstract: Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer.

Abstract: The invention discloses a light-emitting diode including a substrate, a main stack structure, a plurality of secondary pillars, a transparent insulating material, a transparent conducting layer, a first electrode and a second electrode. The pillars are formed on the substrate and surrounding the main stack structure. The main stack structure and each of the pillars has a first conducting-type semiconductor layer, a luminescing layer, and a second conducting-type semiconductor layer formed on the substrate in sequence. The transparent insulating material fills the gaps between the pillars and is as high as the pillars. The transparent conducting layer is coated on the main stack, the pillars and the transparent insulating material. The first electrode is formed on the transparent conducting layer and second electrode is formed on the first conducting-type semiconductor layer.

Abstract: A speaker is disclosed. A speaker includes a fixing part (500) fastened to a base frame; a motion part moved (400) with respect to the fixing part by an electromagnetic force; a vibration plate (200) that vibrates in communication with the motion part; and a guide member (800) provided between the motion part (400) and the vibration plate (200). Therefore, according to the present invention, a speaker capable of reproducing a high quality sound and high power with a slim design may be embodied.

Abstract: The present invention provides a thin film transistor having high performance in a liquid crystal display, and a manufacturing method of a liquid crystal display according to an exemplary embodiment of the present invention that includes: forming a gate line including a gate electrode on a substrate; forming a gate insulating layer on the gate line; forming a data line including a source electrode and a drain electrode facing the source electrode on the gate insulating layer; forming a partition defining a pixel area and having an opening region exposing the gate insulating layer on the gate electrode, the source electrode and the drain electrode on the gate line, and the data line and the drain electrode; forming a semiconductor in the opening region; forming a color filter in the pixel area defined by the partition; and forming a pixel electrode connected to the drain electrode on the color filter.

Abstract: The invention provides a technique to manufacture a highly reliable semiconductor device and a display device at high yield. As an exposure mask, an exposure mask provided with a diffraction grating pattern or an auxiliary pattern formed of a semi-transmissive film with a light intensity reducing function is used. With such an exposure mask, various light exposures can be more accurately controlled, which enables a resist to be processed into a more accurate shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in the same step into different shapes in accordance with desired performances. As a result, thin film transistors with different characteristics, wires in different sizes and shapes, and the like can be manufactured without increasing the number of steps.

Abstract: There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.

Abstract: A liquid crystal display and a method of manufacturing the same are provided. The liquid crystal display includes an insulating substrate, a gate electrode formed on the insulating substrate, an oxide semiconductor layer formed on the gate electrode, an etch stopper formed on the oxide semiconductor layer in a channel area, a common electrode formed on the insulating substrate, source and drain electrodes separated from each other on the etch stopper and extending to an upper portion of the oxide semiconductor layer, a passivation layer formed on the etch stopper, the common electrode, the source and drain electrodes, and a pixel electrode formed on the passivation layer and connected to the drain electrode.

Abstract: A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads.

Abstract: An audio output circuit includes a port attenuation circuit, which is configured to convert an abrupt dc voltage offset transition between a pair of audio signals received in sequence at an input thereof into a more gradual transition. This conversion is achieved by performing, in sequence, a ramp-to-mute operation on a first of the pair of audio signals and a ramp-from-mute operation on a second of the pair of audio signals. The ramp-to-mute operation includes ramping an output of the audio output circuit from a dc voltage offset associated with the first of the pair of audio signals to a reference dc voltage offset. The ramp-from-mute operation includes ramping the output of the audio output circuit from the reference dc voltage offset to a dc voltage offset associated with the second of the pair of audio signals. These ramping operations may be performed using voltage steps having uniform step size.

Abstract: An organic light emitting diode display includes a plurality of pixels. Each pixel includes a light emitting element and a driving transistor coupled to the light emitting element. The pixels may be arranged in a matrix. The pixels include first pixels, second pixels, and third pixels, the driving transistors of the first to the third pixels occupy different areas, and the light emitting elements of the first to the third pixels occupy substantially equal area.

Abstract: A semiconductor device includes a first compound semiconductor layer having a two-dimensional carrier gas channel, a second compound semiconductor layer which functions as a barrier layer and is arranged above the first compound semiconductor layer, a first main electrode connected to one end of the two-dimensional carrier gas channel, and a second main electrode connected to another end of the two-dimensional carrier gas channel, these ends being separated, wherein a compound ratio of an elemental compound of the second compound semiconductor layer is different in a direction of the two-dimensional carrier gas channel between the first main electrode and the second main electrode.

Abstract: Failure light emission of an EL element due to failure film formation of an organic EL material in an electrode hole 46 is improved. By forming the organic EL material after embedding an insulator in an electrode hole 46 on a pixel electrode and forming a protective portion 41b, failure film formation in the electrode hole 46 can be prevented. This can prevent concentration of electric current due to a short circuit between a cathode and an anode of the EL element, and can prevent failure light emission of an EL layer.

Abstract: A III-nitride device having a support substrate that may include a first silicon body, a second silicon body, an insulation body interposed between the first and second silicon bodies, and a III-nitride body formed over the second silicon body.

Abstract: A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.

Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.

Abstract: This image sensor is so formed as to control at least either the potential of a portion of a transfer channel corresponding to a third electrode or the potential of another portion of the transfer channel corresponding to a fourth electrode to be lower than the potentials of portions of the transfer channel corresponding to a first electrode and a second electrode respectively in a signal charge transferring operation and a signal charge increasing operation.

Abstract: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The semiconducting layer includes a carbon nanotube film, a plurality of carbon nanotubes in the carbon nanotube film oriented along a direction from the source electrode to the drain electrode.

Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is a neutralized acid having a pKa of 5 or less, wherein at least 90% of the acid groups are neutralized. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: An LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%, and wherein at least one of the Type II interfaces is within a pn junction. Alternately, an LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%. The Type II interfaces may include interfaces from a layer which is an electron quantum well and not a hole quantum well, interfaces to a layer which is a hole quantum well and not an electron quantum well; and interfaces that satisfy both conditions simultaneously. The Type II interfaces may be within a pn or pin junction or not within a pn or pin junction. In the later case, emission from the Type II interfaces may be photopumped by a nearby light source. The LED may be a white or near-white light LED.