Patents Examined by Walter H Swanson
  • Patent number: 10580777
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 10580850
    Abstract: A display device includes a substrate, a first insulating layer, a power lines, and connection lines. The substrate includes a peripheral area adjacent to at least one side of a pixels area. The first insulating layer including one or more contact holes. The power line is in the peripheral area and provides a driving voltage to pixels. The power line includes a first metal layer on the substrate and a second metal layer connected to the first metal layer through the contact hole. The connection lines extend to the peripheral area from the pixels and overlap part of the power line. The power line includes a first area in which the first and second metal layers are electrically connected through the contact hole. The connection line does not overlap the first area of the power line.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Hyun Lee, Deuk Jong Kim, Shin Jeong Han
  • Patent number: 10566294
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV have bottom ends at the same height.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 18, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10566577
    Abstract: An organic light emitting display device and an organic light emitting display apparatus are provided. The organic light emitting display device includes a first electrode and a second electrode disposed opposite to each other, a light emitting layer positioned between the first electrode and the second electrode, and a capping layer positioned on a surface of a side of the second electrode far away from the light emitting layer, the capping layer is formed as a single layer or superposition of a plurality of layers, the at least one layer of the capping layer is a composite layer, and the composite material of the composite layer comprises an organic material and a metal dopant.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 18, 2020
    Assignees: Shanghai Tianma AM-OLED Co., Ltd., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yinhe Liu, Wei He, Xiangcheng Wang, Yuji Hamada, Jinghua Niu, Qing Zhu
  • Patent number: 10566402
    Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a plurality of pixels, each pixel including a driving circuit that includes a driving transistor and a storage capacitor electrically connected to the driving transistor. The driving transistor includes a driving active layer and a first electrode, the first electrode insulated from the driving active layer and disposed over at least a portion of the driving active layer. The storage capacitor includes a first capacitor including the first electrode and a second electrode facing the first electrode and a second capacitor comprising the second electrode and a third electrode facing the second electrode.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seunghwan Cho, Sangho Park, Donghwan Shim, Kiwan Ahn, Joosun Yoon
  • Patent number: 10566308
    Abstract: A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Kenshi Kai, Kazuya Adachi
  • Patent number: 10559732
    Abstract: A surface-mounted light-emitting device is fabricated by epitaxial growth: forming the LED epitaxial structure over a growth substrate through epitaxial growth; chip fabrication: determining P and N electrode regions and an isolating region over the LED epitaxial structure surface and fabricating the P and N electrode pads and the insulator over the P and N electrode regions and the isolating region, wherein the P and N electrode pads have sufficient thicknesses to support the LED epitaxial structure, and the insulator is formed between the P and N electrode pads to prevent the P and N electrode pads from a short circuit; removing the growth substrate and unitizing the LED epitaxial structure to form the chip; and SMT packaging: providing the supporting substrate and directly mounting the P and N electrode pads of the chip over the supporting substrate through SMT packaging to thereby form the surface-mounted LED light-emitting device.
    Type: Grant
    Filed: December 3, 2016
    Date of Patent: February 11, 2020
    Assignee: XIAMEN SANAN OPTO ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shaohua Huang, Xiaoqiang Zeng, Chih-Wei Chao
  • Patent number: 10553815
    Abstract: An organic light emission display device and an encapsulation method therefor are provided. The organic light emission display device includes a base substrate, and an organic light emission diode, a barrier layer and an organic thin film encapsulation layer which are disposed on the base substrate. The organic light emission display device further includes a detection layer disposed on the base substrate; and the detection layer is configured to contact with the organic thin film encapsulation layer and make a change in the case that the organic thin film encapsulation layer overflows the barrier layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 4, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Fashun Li, Ang Xiao, Lina Wang
  • Patent number: 10553682
    Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Zheng Xu
  • Patent number: 10553600
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Patent number: 10550622
    Abstract: The boarding area (A, B, C) of a transport means is divided into at least two gates (1, 2, 3), the maximum person capacity of which corresponds, respectively, to the maximum capacity of the largest transport device (9) that is accessible via the boarding area (A, B, C). Entrance into the gates (1, 2, 3) is effected via at least one separating device (4) connected with a control system (5) for the purpose of data communication. Entrance into each gate (1, 2, 3) is not possible once the number of persons in the gate (1, 2, 3) specified by the control system (5) for the current boarding operation is reached, or while the persons inside the gate (1, 2, 3) board the transport car. The number of persons in each gate (1, 2, 3) for the current boarding operation is determined by the control system (5) in dependence upon the transport demand in subsequent intermediate stations ahead of an end station, provided such intermediate stations are present, and of the free capacity of the arriving transport car (9).
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: February 4, 2020
    Assignee: SKIDATA AG
    Inventors: Richard Kobler, Thomas Hulan
  • Patent number: 10546985
    Abstract: Illumination devices based on quantum dot technology and methods of making such devices are described. An illumination device includes a substrate having a plurality of microLEDs, a beam splitter, and a film having a plurality of quantum dots. The beam splitter includes a plurality of layers and is disposed between the substrate and the film having the plurality of quantum dots.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 28, 2020
    Assignee: Nanosys, Inc.
    Inventor: Ernest C. Lee
  • Patent number: 10541198
    Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien Lin Chang Chien, Chin-Li Kao, Chang Chi Lee, Chih-Pin Hung
  • Patent number: 10541247
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Wataru Sakamoto
  • Patent number: 10535518
    Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 14, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Danny M. Kim, Rongming Chu, Yu Cao, Thaddeus D. Ladd
  • Patent number: 10529748
    Abstract: There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer (11) and a second material layer (12) (laser light irradiation, pressure application, or the like) is performed before peeling, and then peeling is conducted by physical means. Therefore, sufficient separation can be easily conducted in an inner portion of the second material layer (12) or an interface thereof.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: January 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Shunpei Yamazaki
  • Patent number: 10529668
    Abstract: Forming a groove in a dicing region so as to expose a conductive pattern material on a side surface, closer to a first side of each of mounting regions, of a substrate; when forming a first sealing portion enclosing a wireless region and a second sealing portion enclosing an antenna region adjacent to the wireless region on a side of a second side of each of the mounting regions, reducing a thickness in a height direction such that a thickness of the second sealing portion becomes smaller in thickness than a thickness of the first sealing portion; forming a shielding film such that a scattered matter made of a conductive material is allowed to pass through an upper surface of the second sealing portion, to be deposited onto the conductive pattern material exposed on a side surface of the substrate; and separating the substrate into the mounting regions individually.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kenzo Kitazaki, Takehiko Kai, Masaya Shimamura, Mikio Aoki, Jin Mikata, Taiji Ito
  • Patent number: 10529787
    Abstract: Disclosed are a backplane substrate, which is devised to attain circuit characteristics for realizing sufficient gradation even in smaller pixels of a super-high-resolution structure, a manufacturing method for the same, and an organic light-emitting display device using the same, inn the backplane substrate, a driving thin-film transistor has a stack structure different from that of other thin-film transistors so that only the S-factor of the driving thin-film transistor is increased.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 7, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Kum-Mi Oh, Shun-Young Yang, Min-Seong Yun
  • Patent number: 10529939
    Abstract: An organic light-emitting device is configured such that, in a plurality of stacks in which the optical distance is adjusted using the thickness of an emission layer, the structure of the emission layer is changed to reduce the drive voltage and increase the lifespan thereof, and an organic light-emitting display device using the same.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 7, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Su-Hyeon Kim
  • Patent number: 10522435
    Abstract: On a conductive plate of an insulated substrate, one open end of a main body part of a cylindrical contact member is bonded by solder. In a hollow part of a hollow cylinder shaped external electrode terminal, a part of the other open end side of the main body part of the cylindrical contact member is inserted from an open end of the external electrode terminal. The other end of the external electrode terminal is separated into branches by cuts inserted in a through-hole insertion part. A column surface of the outside of the branches of the external electrode terminal has an arc shape. Pressure in a direction from inside the external electrode terminal toward the outside is applied to the branches of the through-hole insertion part by an auxiliary wedge. With such a configuration, assembly defects accompanying connection of the external electrode terminal and other members may be eliminated.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kazuya Adachi