Patents Examined by Walter H Swanson
-
Patent number: 10770289Abstract: A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.Type: GrantFiled: March 7, 2018Date of Patent: September 8, 2020Assignee: Massachusetts Institute of TechnologyInventor: Jeehwan Kim
-
Patent number: 10763207Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.Type: GrantFiled: March 28, 2018Date of Patent: September 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jorge A. Kittl, Ganesh Hegde, Harsono Simka
-
Patent number: 10763337Abstract: A method of forming a gate-all-around device includes forming a gate electrode layer over a substrate, patterning the gate electrode layer to form a conical frustum-shaped gate electrode, etching the conical frustum-shaped gate electrode to form a through hole extending through top and bottom surfaces of the conical frustum-shaped gate electrode, and after etching the conical frustum-shaped gate electrode, forming a nanowire in the through hole in the conical frustum-shaped gate electrode.Type: GrantFiled: June 17, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
-
Patent number: 10756044Abstract: A fan-out semiconductor package includes a connection member including an insulating layer, a redistribution layer, and conductive vias penetrating through the insulating layer and connected to the redistribution layer, and a semiconductor chip and a passive chip disposed on the connection member and electrically connected to the redistribution layer. A conductive via connected to the passive element among the conductive vias has a multiple via shape in which a plurality of sub-vias, a width of each sub-via is decreased in a thickness direction, and end portions of the plurality of sub-vias are integrated with each other.Type: GrantFiled: March 30, 2018Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sang Hyuck Oh
-
Patent number: 10748914Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.Type: GrantFiled: December 13, 2017Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy, Manuj Nahar
-
Patent number: 10741707Abstract: Photodetectors and methods of forming the same include a first electrode. A carbon nanotube film is formed on the first electrode. A first graphene sheet is formed on the carbon nanotube film. A second graphene sheet is configured to exert an electrical field on the first graphene sheet that changes an electrical property of the first graphene sheet.Type: GrantFiled: March 23, 2018Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abram L. Falk, Kuan-Chang Chiu, Damon B. Farmer, Shu-Jen Han
-
Patent number: 10741638Abstract: A semiconductor device includes a doped Si base substrate, one or more device epitaxial layers formed over a main surface of the doped Si base substrate, a diffusion barrier structure, and a gate formed above the diffusion barrier structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si formed in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers.Type: GrantFiled: August 8, 2018Date of Patent: August 11, 2020Assignee: Infineon Technologies Austria AGInventors: Martin Poelzl, Robert Haase, Maximilian Roesch, Sylvain Leomant, Andreas Meiser, Bernhard Goller, Ravi Keshav Joshi
-
Patent number: 10741793Abstract: A method for preparing a light emitting device comprising: disposing an electron-injection layer comprising a metal oxide on a cathode, disposing a first layer adjacent the electron-injection layer, the first layer comprising a small molecule material with a bandgap of at least about 3 eV capable of blocking holes, forming an emissive layer comprising quantum dots capable of emitting blue light upon excitation at a surface of the first layer opposite the electron-injection layer; disposing a second layer comprising a material capable of transporting holes and blocking electrons with a bandgap of at least about 3 eV adjacent a surface of the emissive layer opposite the first layer, and disposing an anode over the second layer. A light-emitting device is also disclosed.Type: GrantFiled: July 3, 2014Date of Patent: August 11, 2020Assignee: SAMSUNG RESEARCH AMERICA, INC.Inventors: Yuhua Niu, Peter T. Kazlas
-
Patent number: 10741627Abstract: An organic light emitting diode (OLED) display includes a substrate, a thin film transistor on the substrate, an organic light emitting diode on the thin film transistor, and including a first electrode connected with the thin film transistor, and a black organic layer between the thin film transistor and the first electrode, and including a black protrusion spaced from the first electrode.Type: GrantFiled: June 8, 2017Date of Patent: August 11, 2020Assignee: Samsung Display Co., Ltd.Inventors: Jin-Soo Jung, Hyeok Jin Lee, Jun Woo Lee, Baek Kyun Jeon
-
Patent number: 10741477Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.Type: GrantFiled: March 23, 2018Date of Patent: August 11, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
-
Patent number: 10734389Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: GrantFiled: October 8, 2019Date of Patent: August 4, 2020Assignee: SK hynix Inc.Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
-
Patent number: 10734611Abstract: The present disclosure relates to an organic light emitting diode display device including: a substrate having an emitting area and a non-emitting area; an insulating layer on the substrate, the insulating layer including a plurality of convex portions, a plurality of connecting portions and at least one wall in the emitting area, a height of the at least one wall is greater than a height of the plurality of convex portions; a first electrode on the substrate; an emitting layer on the first electrode; and a second electrode on the emitting layer, the first electrode, the emitting layer and the second electrode constituting a light emitting diode.Type: GrantFiled: September 27, 2017Date of Patent: August 4, 2020Assignee: LG Display Co., Ltd.Inventors: Hyun-Soo Lim, Kang-Ju Lee, Soo-Kang Kim, Won-Hoe Koo, Min-Geun Choi
-
Patent number: 10734347Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.Type: GrantFiled: May 1, 2019Date of Patent: August 4, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
-
Patent number: 10727125Abstract: A bonding structure for a flexible screen and a manufacturing method are provided a flexible screen and a chip mounted on a surface of the flexible screen are arranged on the bonding structure for the flexible screen, and a bonding area for bonding the chip is arranged on the flexible screen, and a flexible protective layer is coated in the bonding area, and the flexible protective layer surrounds around the chip. Compared with the prior art, by forming the flexible protective layer with different hardness around the chip, the stress generated around the chip during the peeling-off are greatly dispersed, a stress gradient is formed, the stress concentration at the position closely adjacent to the periphery of the chip is avoided, the risk of the circuits around the chip being pulled broken can be reduced, and the peeling-off yield of the flexible screen can be finally increased.Type: GrantFiled: November 30, 2016Date of Patent: July 28, 2020Assignee: Kunshan New Flat Panel Display Technology Center Co., Ltd.Inventors: Xiuyu Zhang, Baoyou Wang, Pengle Dang, Liwei Ding, Xiaobao Zhang, Hui Zhu
-
Patent number: 10727429Abstract: An electronic device includes a first electrode 31, a light emitting/light receiving layer 20 formed on the first electrode 31, and a second electrode 32 formed on the light emitting/light receiving layer 20. The light emitting/light receiving layer 20 and/or the second electrode 32 is covered by an insulating layer 40 including a metal oxide that contains, as a main component, zinc oxide, while containing, as accessory components, at least two materials selected from the group consisting of aluminum oxide, magnesium oxide, niobium oxide, titanium oxide, molybdenum oxide and hafnium oxide.Type: GrantFiled: June 20, 2016Date of Patent: July 28, 2020Assignee: Sony CorporationInventors: Toshiki Moriwaki, Mari Ichimura
-
Patent number: 10720599Abstract: An organic light-emitting display device including a partition wall is provided. The organic light-emitting display device includes a first bank insulating layer covering an edge of a lower electro and a second bank insulating layer supporting the partition wall. The second bank insulating layer is completely spaced apart from the first bank insulating layer. The first bank insulating layer facing the second bank insulating layer is completely covered by an upper electrode which is disposed on a portion of the lower electrode exposed by the first bank insulating layer.Type: GrantFiled: August 30, 2017Date of Patent: July 21, 2020Assignee: LG Display Co., Ltd.Inventor: Kyung-Man Kim
-
Patent number: 10712728Abstract: A motor control apparatus includes a memory and a setting selector. The memory is configured to store setting items each relating to a motor, and the setting sequence to sequentially set the setting items. The setting selector is connected to the memory and configured to select a newly selected item from among the setting items based on the setting sequence, a user input, and a currently selected item of the setting items.Type: GrantFiled: November 20, 2015Date of Patent: July 14, 2020Assignees: KABUSHIKI KAISHA YASKAWA DENKI, YASKAWA AMERICA, INC.Inventors: Yasushi Kibe, William Phillips, Christopher Jaszczolt, Micah Stuedemann
-
Patent number: 10714406Abstract: The module (PM1) has an architecture with 3D stacking of the electronic power switching chips (IT, ID) and comprises first and second dielectric substrates (SH, SL) that are intended to come into thermal contact with first and second heat sinks (DH, DL), respectively, at least one pair of first and second stacked electronic power switching chips (ITHS, IDHS; ITHS, IDHS) and a common intermediate substrate (SC), the first and second electronic power switching chips being sandwiched between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate, respectively. According to the invention, the common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of the electronic power switching chips and at least one.Type: GrantFiled: April 9, 2018Date of Patent: July 14, 2020Assignee: INSTITUT VEDECOMInventors: Hadi Alawieh, Menouar Ameziani
-
Patent number: 10714661Abstract: A light-emitting apparatus includes: a solid-state light source; and a wavelength convertor. The solid-state light source emits first light including green light with a peak wavelength in a range of 480 to 550 nm, inclusive. The wavelength convertor contains a red phosphor including Ce as a luminescent center. The red phosphor is excited by at least part of the green light to emit second light. The second light has a spectrum with a peak wavelength in a range of 600 to 700 nm, inclusive. The red phosphor contains a nitride or an oxynitride as a host material.Type: GrantFiled: March 23, 2018Date of Patent: July 14, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Mitsuru Nitta, Nobuaki Nagao, Yasuhisa Inada
-
Patent number: 10707326Abstract: A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.Type: GrantFiled: February 22, 2019Date of Patent: July 7, 2020Assignee: International Business Machines CorporationInventors: Chi-Chun Liu, Sanjay Mehta, Luciana Meli, Muthumanickam Sankarapandian, Kristin Schmidt, Ankit Vora
