Abstract: The module (PM1) has an architecture with 3D stacking of the electronic power switching chips (IT, ID) and comprises first and second dielectric substrates (SH, SL) that are intended to come into thermal contact with first and second heat sinks (DH, DL), respectively, at least one pair of first and second stacked electronic power switching chips (ITHS, IDHS; ITHS, IDHS) and a common intermediate substrate (SC), the first and second electronic power switching chips being sandwiched between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate, respectively. According to the invention, the common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of the electronic power switching chips and at least one.

Abstract: A light-emitting apparatus includes: a solid-state light source; and a wavelength convertor. The solid-state light source emits first light including green light with a peak wavelength in a range of 480 to 550 nm, inclusive. The wavelength convertor contains a red phosphor including Ce as a luminescent center. The red phosphor is excited by at least part of the green light to emit second light. The second light has a spectrum with a peak wavelength in a range of 600 to 700 nm, inclusive. The red phosphor contains a nitride or an oxynitride as a host material.

Abstract: A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.

Abstract: A display device includes: a display panel; and a color conversion panel overlapping the display panel, wherein the color conversion panel includes a red color conversion layer and a green color conversion layer including a semiconductor nanocrystal, and a transmissive layer; a red color filter overlapping the red color conversion layer; a green color filter overlapping the green color conversion layer; and a blue color filter overlapping the transmissive layer and a light blocking member, and the light blocking member includes at least one of a blue dye and a blue pigment.

Abstract: A set of test key layout including multiple test keys and method of monitoring layout pattern misalignments using the test keys is provided. Each test key is composed of a testing electrode, an operating voltage (Vdd) line and a grounding voltage (Vss) line, wherein the patterns of test keys are defined by an overlapped portion of a first exposure pattern and a second exposure pattern, and the position of testing electrode is shifted sequentially in one direction in order of the test keys.

Abstract: The present application discloses an array substrate having a display area and a peripheral area. The array substrate includes a plurality of first thin film transistors respectively in a plurality of subpixels in the display area; and a plurality of second thin film transistors in the peripheral area, an oxygen content in active layers of the plurality of first thin film transistors being higher than that in active layers of the plurality of second thin film transistors.

Abstract: A display substrate and an OLED display device, the display substrate including a water absorbing structure disposed on the display substrate that is configured to be capable of absorbing moisture in the display substrate. In the embodiments of the present invention, by providing a water absorbing structure in the display substrate, it is possible to protect the organic luminescent unit from moisture released in the process of manufacturing and operating the display substrate, enhance the performance of the OLED display device and prolong the service life of the OLED display device.

Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.

Abstract: A semiconductor power device formed in a semiconductor substrate that includes a plurality of trenches formed at a top portion of the semiconductor substrate. The trenches extend laterally across the semiconductor substrate along a longitudinal direction and each trench has a nonlinear portion thus the nonlinear portion has a trench sidewall perpendicular to the longitudinal direction of the trench. A plurality of trench bottom dopant regions are formed below the trench bottom surface. A sidewall dopant region is formed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Abstract: An imaging device includes a first chip (12). The first chip includes a first pixel (21) and a second pixel (21). The first pixel includes a first anode region (31) and a first cathode region (32), and the second pixel includes a second anode region (31) and a second cathode region (32). The first chip includes a first wiring layer (23). The first wiring layer includes a first anode electrode (37), a first anode via (38) coupled to the first anode electrode (37) and the first anode region (31), and a second anode via (38) coupled to the first anode electrode (37) and the second anode region (31).

Abstract: The present disclosure provides a schottky barrier rectifier, comprising: a communication layer; a drift layer provided on a side of the communication layer and forming a heterojunction structure together with the communication layer; anode metal provided on a side of the drift layer away from the communication layer; and cathode metal provided on a side of the communication layer away from the drift layer. The drift layer is provided with a first area, which extends in a direction of thickness thereof, between a surface of the drift layer away from the communication layer and a surface thereof close to the communication layer, the first are a containing a first metal element and the content of the first metal element in the first area changing in the direction of thickness. The rectifier of the present disclosure uses polarized charges formed by a heterojunction, and thus the breakdown voltage of devices may be improved.

Abstract: An imaging device includes: pixels arranged one-dimensionally or two-dimensionally, each of the pixels including an electrode that is electrically connected to the other pixels, a charge capturing unit that is separated from the other pixels, and a photoelectric conversion layer that is located between the electrode and the charge capturing unit, the photoelectric conversion layer being continuous among the pixels. The photoelectric conversion layer contains semiconductor carbon nanotubes, and one of a first substance and a second substance, the first substance having an electron affinity larger than that of the semiconducting carbon nanotubes, the second substance having a ionization energy smaller than that of the semiconductor carbon nanotubes.

Abstract: An organic light emitting diode comprises a hole transport layer, an emissive layer, and an electron transport layer. The hole transport layer and optionally the electron transport layer is made of a material having a refractive index having a specific anisotropy.

Abstract: An optical wavelength conversion member including a polycrystalline ceramic sintered body containing, as main components, Al2O3 crystal grains and crystal grains of a component represented by formula A3B5O12:Ce, wherein A is at least one element selected from Sc, Y and lanthanoids (except for Ce), and B is at least one element selected from Al and Ga. Further, the following relations are satisfied: 0%?X?25%, 9%?Y?45%, and 48%?Z?90%, wherein X represents a proportion corresponding to the ratio a/N, Y represents a proportion corresponding to the ratio b/N, and Z represents a proportion corresponding to the ratio c/N and a, b, c and N are as defined herein. Also disclosed is a light-emitting device including the optical wavelength conversion member.

Abstract: In some examples, a device comprises an integrated circuit comprising a first transistor and a second transistor. The device further comprises an inductor comprising a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is electrically connected to the first transistor and the second transistor. The device further comprises at least five electrical connections on a first side of the device.

Abstract: A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.

Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.