Abstract: A resin molding device, resin molding method and resin molded product capable of guiding a sink to an optional position to perform a precise molding. A resin molding metal mold includes a gate formed in the central part of a cavity, a stepped part increasing the opening diameter of the cavity in the circumferential direction orthogonal to the flowing direction of a molten resin introduced into the cavity from the gate, and a fine outside air inlet part circumferentially formed on the outer part from the stepped part. The outside air inlet part is formed of a porous material and allowed to communicate with the outside of the resin molding metal mold through a communicating passage.

Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.

Abstract: A method of manufacturing a semiconductor device that suppresses emergence of a waste in an isolation trench formation process is to be provided. The method comprises forming an isolation trench having a predetermined depth from a surface of a semiconductor substrate; forming a dielectric layer on the surface of the semiconductor substrate including the isolation trench; filling the isolation trench with a CVD layer; removing the dielectric layer except a portion in the isolation trench by an etching; sequentially forming an insulating layer and a conductive layer; forming a resist defining a pattern which covers via the conductive layer a portion of the insulating layer in contact with the dielectric layer; and performing an anisotropic etching on the resist to thereby remove a portion of the conductive layer exposing a surface thereof.

Abstract: The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device capable of improving the film quality of a dielectric film. The method includes the steps of providing a semiconductor substrate having a storage node contact; forming a metal storage electrode on the substrate; forming a dielectric film using any one chosen from a group including a single film made of HfO2, a single film made of Al2O3, and a lamination film made of HfO2 and Al2O3 on the metal storage electrode; performing CF4 plasma treatment on the dielectric film; and forming a metal plate electrode on the dielectric film.

Abstract: A method for forming a dopant in a substrate, by accumulating at least one dopant species in an asher chamber and forming the accumulated dopant species on an exposed portion of the substrate. A target concentration for the plasma chamber dopant species is determined by test or measurement. The asher is used to form the dopant species on the substrate, and the dopant species is driven into the substrate. A threshold voltage is measured on the substrate to verify or confirm that a proper dopant level has been achieved.

Abstract: For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film successively over a gate insulating film disposed over the main surface of a semiconductor substrate, and patterning them to form a gate electrode having a stacked structure consisting of the polycrystalline silicon film and tungsten silicide film. The polycrystalline silicon film has two regions, one region formed by an impurity-doped polycrystalline silicon and the other one formed by non-doped polycrystalline silicon. The tungsten silicide film is deposited so that the resistivity of it upon film formation would exceed 1000 ??cm.

Abstract: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The resin is provided in the peripheries of the protruding electrodes so as to contact each of the protruding electrodes while not contacting a semiconductor chip.

Abstract: The present invention relates to a method for dividing a substrate into a number of individual chip parts, comprising the steps of: forming a number of chip parts in the substrate, comprising, for each chip part, of arranging recesses in the substrate for containing fluid; arranging one or more breaking grooves in the substrate along individual chip parts; applying mechanical force to the substrate to break the substrate along the breaking grooves. The invention also relates to a substrate as well as a chip part.

Abstract: A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.

Abstract: A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdown during a programming operation by maintaining a breakdown voltage above a programming voltage. The breakdown voltage is, at least partially, increased by forming a p-doped region (140) within a semiconductor substrate (102), and forming a drain region (166) of the OTP EPROM (100) within the p-doped region (140).

Abstract: A method and apparatus for forming a barrier metal layer in semiconductor devices are disclosed. A disclosed method for forming a barrier metal layer in a semiconductor device forms an interlayer insulating layer on a front face of a semiconductor substrate having a contact area and patterns the interlayer insulating layer to open the contact area. The disclosed method further places the semiconductor substrate in a chamber, injects reactant gas and precursor into the chamber, transforms the gas into plasma gas and causes the plasma gas to react with the precursor to form a single TiSiN film covering the contact area.

Abstract: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region.

Abstract: A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etching process. If desired, the chalcogenide structure may be implemented in series with a semiconductor device such as a diode or a selecting transistor. The diode drives a current through the chalcogenide structure. The selecting transistor drives a current through the chalcogenide structure when enabled by a voltage at a gate terminal of the selecting transistor. The selecting transistor has a gate terminal, a source terminal, and a drain terminal; the gate terminal may be operatively coupled to a word line of a memory array, the source terminal may be operatively coupled to a drive line of the memory array, and the drain terminal may be operatively coupled to a bit line of the memory array.

Abstract: The present invention is a method and system for non-intrusively dispatching service requests in a service node nested in a service topology. The method can include receiving a service request in the service node and identifying a requested operation and corresponding parameters for the requested operation from the received service request. A port end point address can be obtained for the requested operation and a service list can be located for the requested operation. It can be determined whether the service node is a destination hub. If so, an operation corresponding to THE service request can be invoked. Otherwise, a service node at a different level in the service topology can be selected and the foregoing process can be recursively performed.

Abstract: One embodiment of the invention is a method for void-free filling with a metal or an alloy inside openings by electrochemical deposition (ECD), said method including steps of: (a) providing a substrate with at least one opening and a field surrounding the at least one opening, said at least one opening having a bottom and sidewalls surfaces, said substrate including an electrically conductive surface, said conductive surface including at least the bottom surface of the at least one opening; (b) immersing the substrate in an electrolyte contained in an electrochemical deposition (ECD) cell, the ECD cell including at least one anode and a cathode, wherein the cathode including at least a portion of the conductive surface of the substrate, and wherein the electrolyte includes plating metallic ions and at least one inhibitor additive, said metallic ions and at least one inhibitor additive having concentrations; (c) providing agitation of the electrolyte across the surface of the substrate immersed in the electrol

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conductive-filled gel elastomer or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conductive-filled gel elastomer is applied between a die surface and the inside attachment surface of a crap-style heat sink to eliminate overpressure on the die/substrate interface.

Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.

Abstract: Continuous wave laser apparatus with enhanced processing efficiency is provided as well as a method of manufacturing a semiconductor device using the laser apparatus. The laser apparatus has: a laser oscillator; a unit for rotating a process object; a unit for moving the center of the rotation along a straight line; and an optical system for processing laser light that is outputted from the laser oscillator to irradiate with the laser light a certain region within the moving range of the process object. The laser apparatus is characterized in that the certain region is on a line extended from the straight line and that the position at which the certain region overlaps the process object is moved by rotating the process object while moving the center of the rotation along the straight line.

Abstract: Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad (350) in the substrate but also a surrounding region. Solder (930) wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (910.1, 910.2), with the top layer (910.2) being more solder wettable than the bottom layer (910.1) and the top layer covering only a portion of the bottom layer.