Abstract: A method of fabricating a lead frame for a semiconductor device having a semiconductor chip resin-sealed therein. The lead frame includes a lead to be electrically connected to the semiconductor chip within sealing resin and to be sealed into the sealing resin such that at least a part of its mounting surface is exposed from the sealing resin. The method includes a lead forming step for forming the lead, and a side edge coining step for subjecting a side edge of a sealed surface, which is a surface on the opposite side of the mounting surface, of the lead to coining processing from the side of the sealed surface, to form a slipping preventing portion. The slipping preventing portion is to project sideward from the lead and to have a slipping preventing surface between the mounting surface and the sealed surface of the lead.

Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.

Abstract: An apparatus that includes a first component defining an interior of the apparatus; a first solder composition exterior to the first component; a second solder composition exterior to the first solder composition and the first component; and a second component exterior to the second solder composition, the first solder composition, and the first component.

Abstract: The method includes forming an isolation film on a silicon substrate to define an active region; forming an antireflective film on an entire surface of the substrate containing the isolation film; forming a photosensitive film pattern on the antireflective film while exposing a portion of the isolation film or the active region adjacent to the isolation film; etching the antireflective film, the isolation film, and the substrate by using the photosensitive film pattern as an etching mask to recess the active region; performing a light etch treatment on a substrate resultant without removing the remaining photosensitive film pattern, so as to remove a damaged layer and a carbon pollutant formed on a surface of the recessed active region; and removing the remaining photosensitive film pattern and the antireflective film.

Abstract: The present disclosure relates to a rapid thermal processing system that may be useful for processing semiconductor devices. A flash lamp may be utilized to provide pulse heating of a semiconductor for annealing or other purposes. A sensor may be provided to sense a characteristic of a semiconductor when a pre-pulse is applied to the semiconductor. Subsequent pulses may then be adjusted based on the characteristic sensed by the sensor.

Abstract: A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.

Abstract: A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and second openings respectively and in contact with the conductive layer, providing a memory structure over the first conductive body, providing a protective element over the memory structure, and undertaking processing on the second conductive body.

Abstract: In a lead frame, through holes are formed outside suspending leads and trenches are formed on a back surface along the suspending leads so as to communicate with the through holes. When sealing resin is injected into cavities of a resin molding die, air enters the through holes through air vents and flows out from the through holes by a resin injection pressure in the trenches, making it easier for the sealing resin to enter the through holes. Since the sealing resin leaking to the air vents can be injected into the through holes, it is possible to enhance the bonding force between the sealing resin after curing and the lead frame in the vicinity of the air vents and effect release of the resin molding die, while allowing the sealing resin leaking to the air vents to remain on the lead frame side without remaining within the air vents.

Abstract: A semiconductor device including a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode; wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.

Abstract: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.

Abstract: The speed of the laser scanned by the scanning means such as a galvanometer mirror or a polygon mirror is not constant in the center portion and in the end portion of the scanning width. As a result, the object, for example an amorphous semiconductor film, is irradiated with the excessive energy and therefore there is a risk that the amorphous semiconductor film is peeled. In the present invention, in the case where the laser spot of the energy beam output continuously on the irradiated object is scanned by moving it back and forth with the use of the scanning means or the like, the beam is irradiated to the outside of the element-forming region when the scanning speed of the spot is not the predetermined value, for example when the speed is not constant, and accelerates, decelerates, or is zero, for example in the positions where the scanning direction changes, or where the scanning starts or ends.

Abstract: Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate trench, is etched to expose the remaining substrate region. Thereafter, the exposed portion of the remaining substrate region is removed to form a substantially flat bottom of the gate trench. The recess transistor manufactured by the provided method has the same channel length regardless of the locations of the recess transistor in an active region.

Abstract: A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.

Abstract: Solder is connected to the electrodes of the circuit board by using a temperature profile with a constant fusion temperature, a connection interface strength evaluation test is carried out on the soldered joints to obtain an appropriate reflow range free of decreases in the strength at the connection interface. On the basis of the appropriate reflow range obtained and using as the basis the chemical compound thickness which is determined uniquely by heat load, an appropriate reflow range in an optional temperature profile with one temperature peak is obtained. By carrying out connection in this appropriate reflow range, soldered joints can be obtained without decreases in the connection interface strength in the large-scale production stage.

Abstract: An IC chip mounting method which mounts two or more IC chips on a base, includes: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by dividing the wafer into IC chips by dicing while leaving the tape; positioning the wafer to face the base in such a direction that the mounting surface to be attached to the base faces the base; sequentially pressing the IC chips on the wafer against the base and temporarily fixing the IC chips while the base is being fed in a prescribed one-dimensional direction along the wafer and while the wafer is being moved two-dimensionally along the base; and fixing the IC chips temporarily fixed on the base on the base by heating and pressurizing in a batch manner.

Abstract: A method of fabricating a gate of a transistor device on a semiconductor substrate, includes the steps of placing the substrate in a vacuum chamber of a plasma reactor and introducing into the chamber a process gas that includes oxygen while maintaining a vacuum pressure in the chamber. An oxide insulating layer on the order of several Angstroms in thickness is formed at the surface of the substrate by generating a plasma in a plasma generation region within the vacuum chamber during successive “on” times, and allowing ion energy of the plasma to decay during successive “off” intervals separating the successive “on” intervals, the “on” and “off” intervals defining a controllable duty cycle. During formation of the oxide insulating layer, the duty cycle is limited so as to limit formation of ion bombardment-induced defects in the insulating layer, while the vacuum pressure is limited so as to limit formation of contamination-induced defects in the insulating layer.

Abstract: A dielectric wiring structure and method of manufacture therefor. The wiring structure includes air dielectric formed in a hemisphere. The wiring structure also includes, in embodiments, a method of simultaneously forming a MEMS structure with a transistor circuit using substantially the same steps. The MEMS structure of this embodiment includes freestanding electrodes which are not fixed to the substrate.

Abstract: An image reading apparatus (10) includes a photoelectric conversion element formation substrate (4) having a plurality of photoelectric conversion elements (2) on a reverse surface of an information reading surface, and a supporting substrate (1) bonded by an adhesive resin (5) to the photoelectric conversion element formation substrate (4) so that the supporting substrate (1) is integrated with the photoelectric conversion element formation substrate (4) and faces the plurality of photoelectric conversion elements (2) on the photoelectric conversion element formation substrate (4). With this arrangement, provided is a photoelectric conversion apparatus and manufacturing method of same in which (a) a process of bonding a micro glass sheet is not required and (b) a protrusion of an installation portion toward a surface of a document is eliminated.

Abstract: Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.

Abstract: A photodiode with a semiconductor intrinsic light absorption layer has at least one p-doped light absorption layer or an n-doped light absorption layer, and preferably both. The diode also has a cathode electrode and an anode electrode electrically coupled with the p-doped light absorption layer or the n-doped light absorption layer.