Abstract: A programmable-divider provides a lower-speed transition signal to effect a synchronized load of a new divisor value during a safe-load period of the programmable-divider, such that the division occurs using either the prior divisor value or the new divisor value, only. A combination of in-phase and reverse-phase counter stages are used to position the divisor-independent period of each counter stage so that an edge of at least one of the lower-speed counter-enabling signals occurs during a period when all of the counter stages are in a divisor-independent period. The preferred selection of in-phase and reverse-phase counter stages also maximizes the critical path duration, to allow for the accurate division of very high speed input frequencies.

Abstract: The dual-modulus prescaler circuit for a frequency includes several dividers-by-two of the asynchronous type, connected in series, a phase selector unit (11) inserted between two of the dividers-by-two (10, 12a) and a control unit for supplying first control signals(S0, S1, S2, C1, C2) to the selector unit as a function of a selected mode. Said control unit receives four signals phase shifted by 90° with respect to each other from a first master-slave divider and supplies a selected one of the four phase shifted signals. The selector unit includes a first amplifying branch (21) receiving two first phase shifted signals (F2I, F2Ib), a second amplifying branch (22) receiving two second phase shifted signals (F2Q, F2Qb), and a selection element (23) connected to each branch. The first control signals (S0, S1, S2) are supplied to the first and second branches, and to the selection element for selecting one of the four phase shifted signals (F2) at one output in a determined division period.

Abstract: A real time clock counter includes a serially connected plurality of register units, each register unit having a bit register for storing clock data, a half adder for incrementing the clock data stored in the bit register, and an activation circuit for activating the bit register. Each activation circuit includes a first input for receiving an oscillating timing signal and a second input for receiving a binary carry term from the previous bit register unit's half adder. Each activation circuit also includes an output for outputting a first activation signal or a second activation signal according to the first value and the oscillating timing signal such that when the activation circuit outputs the first activation signal, the bit register is activated, and when the activation circuit outputs the second activation signal, the bit register is not activated, saving power.

Abstract: A method and apparatus are arranged to provide a multi-bit digital signal that represents a normalized percentage of time that a signal is active. The apparatus includes an N-bit counter that is periodically reset to an initialization condition, and a logic block that processes the output of the N-bit counter. The N-bit counter is arranged to evaluate a monitored signal for each cycle of a clock signal, and modify the count accordingly. The logic block is configured to periodically scan the output of the N-bit counter after the expiration of a sampling time interval. The sampling time interval is determined by a timing circuit such as a window counter that is operated from the clock signal. The logic block periodically evaluates the output of the N-bit counter and provides the normalized multi-bit digital signal.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: The invention features a fractional frequency divider including a phase selection device where mutually phase-shifted signals are alternately switched through to a phase output, at the input of the phase selection device; and a control device for selecting individual phases where the control device changes the mutually phase-shifted signals.

Abstract: An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The asynchronous up-down counter also includes a signal bus coupling the up-down control output of a first counter block counting lesser significant bits to the up-down control input of a second counter block counting more significant bits. An up-down control signal output from each of the counter blocks has at least two bits. The up-down control signal may include a first control signal enabling counting operation of the second counter block and a second control signal indicating counting-up and counting-down.

Abstract: A revolution counter; includes a base body having a sensor arrangement and a power supply device which supplies energy to the sensor arrangement, and a rotary element connectable to a revolving member and rotating relative to the base body about a rotation axis. The rotary element includes a magnet arrangement, which so interacts with the power supply device that the sensor arrangement is supplied with energy during each revolution of the rotary element in at least three rotary positions of the rotary element regardless of a rotation speed of the rotary element to thereby allow the sensor arrangement to ascertain a rotary position of the rotary element. In order to prevent a transmission of mechanical forces from the rotary element to the base body, the rotary element is positioned with respect to the base body either without connection to the base body, or held by the base body at three-dimensional play.

Abstract: There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored. To reduce the computing time for saving the data content of the register, while keeping the silicon surface required for the register system as small as possible, the additional storage arrangement includes at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.

Abstract: A revolution counter includes a single sensor which scans movement of a rotary element and generates a raw signal commensurate with a rotary position of the rotary element for ascertaining one of at least three areas of angular ranges. Two of these areas include each a single continuous angular range, whereas a third area includes at least two angular ranges, which interrelate but are separated from one another. A power generation system delivers energy pulses to the sensor, when the rotary element rotates below a minimum value, so that a raw signal can be detected and the corresponding angular range area can be determined. The power generation system and the rotary element are so interconnected as to ascertain for at least part of the thus determined areas of angular ranges, by which of the angular ranges the rotary element is rotated, and to establish the number of revolutions based on the ascertained angular ranges.

Abstract: A machine used for digital counting which can provide multiple output counts. The machine is particularly useful in analog-to-digital (A/D) converters and in digital-to-analog (D/A) converters. The multiple output counts can change in different directions or in the same direction, and are generated using shared circuitry. The invention exploits properties of counting systems to allow A/D and D/A conversions in convenient digital number formats or in multiple different formats. The invention can be used in integrating converters to help eliminate errors such as comparator offset and dielectric absorption while converting and to increase the conversion rate.

Abstract: A method and apparatus for providing of normalizing a bit count is provided. The method comprises counting bits for a first frame, and normalizing a target bit in a target frame using the bits of the frame. The method then comprises counting to the normalized target bit in the target frame.

Abstract: Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.

Abstract: A counting device with control system includes a housing with a rotating wheel therein. The wheel includes a plurality of seats for each item to be counted. Upon deposit of the items into the housing, each item is seated for discharge through a housing aperture, past a sensor operating a counter and onto a conveyor line. A baffle adjacent the housing aperture directs the counted items to one or the other longitudinal side of the conveyor line. A control system controls the baffle position according to a preselected item count. An air pressure system assures a proper seating of each items and discharge through the housing aperture.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

Abstract: A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number. The second number is sign extended one bit to create a second sign extended number. The second sign extended number is subtracted from the first sign extended number to determine a subtraction result. The sign bits for said first number and said second number are examined to determine if they are both ones. If the sign bits for the first number and the second number are both ones, the sign bit of the subtraction result is inverted to create a final result. If the sign bit of the final result is a zero, asserting that the first number is greater than or equal to the second number. Alternatively, if the sign bit of the final result is a one, asserting that the first number is less than the second number.

Abstract: A pedometer including a pedometer body having a measuring mechanism that makes a measurement of a number of steps walked and a display that shows the measurement result; an illumination lamp and a battery installed in the pedometer body; a window provided in the pedometer body so as to allow the light of the illumination lamp to illuminate the outside of the pedometer body; and a power switch provided on the pedometer body and operable from the outside so as to turn on and off the illumination lamp.

Abstract: The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

Abstract: An apparatus and associated method is disclosed for increasing the maximum input frequency of a frequency divider system by altering the division ratio in the frequency divider system. In an exemplary form, the apparatus includes an electrical mixer circuit to combine an internal and an external frequency input signals into a combination frequency signal and a frequency divider circuit to receive the combination frequency signal and to frequency divide the combination frequency signal by a predetermined number, a signal splitter and a directional coupler in operative to receive the divided frequency signal and to generate an output frequency signal and a feedback frequency signal wherein the feedback frequency signal is identical in frequency to the output frequency signal and becomes the internally inputted frequency signal for the mixer. In this way the maximum input frequency of the frequency divider system can be advantageously increased.