Patents Examined by Wambach
  • Patent number: 6542568
    Abstract: A system for rewarding and encouraging compliance with a predetermined personal hygiene standard in a hygiene compliance program. The system comprises a fluid dispenser. The fluid dispenser includes an actuator. A sensor is connected to the actuator. A processor in electrical communication with the sensor. The processor is configured to increment a count when the sensor is actuated, relate the count to the identification code, and compare the count to a predetermined number.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: April 1, 2003
    Assignee: Ecolab Inc.
    Inventors: Ronald Bruce Howes, Jr., James L. Copeland
  • Patent number: 6535569
    Abstract: A synchronous counter includes at least three or more flip-flops having a chain structure, and at least two or more 2-input EXOR gates interposed in the chain structure. The number of stages of gates interposed between the output of one among the flip-flops and the input of another is one stage of a 2-input EXOR gate even in a critical path thereby shortening the critical path.
    Type: Grant
    Filed: January 9, 2001
    Date of Patent: March 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masami Nakajima, Hiroyuki Kondo
  • Patent number: 6522711
    Abstract: In a variable frequency divider formed of a latch train, a frequency division ratio is set through selective invalidating a feedback signal to a first stage latch from the last stage latch. A size of MOS (metal-insulator-semiconductor) transistors for switching the division ratio is made larger than that of other MOS transistors in differential stages in the last stage latch circuit. Further, differential signals are transmitted as feedback signals to the first stage latch circuit. A F/(F+1) prescaler which operates stably with a low current consumption under a low power supply voltage condition is implemented.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: February 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideyuki Wakada, Naoyuki Kato, Hisayasu Satoh, Hiroshi Komurasaki
  • Patent number: 6519310
    Abstract: An integrated circuit chip includes counters. Each one of the counters counts data events, There are a plurality of registers associated with the counters. At lease one of the registers controls the stopping, starting and counting of an associated counter. A command trigger issues a command to the register upon the detection of a hardware event. The command initiates the starting, stopping or counting of the counter associated with the register.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: February 11, 2003
    Assignee: Intel Corporation
    Inventor: James S. Chapple
  • Patent number: 6519311
    Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: February 11, 2003
    Assignee: Broadcom Corporation
    Inventor: Jun Cao
  • Patent number: 6504890
    Abstract: A cash counting apparatus for cashbox comprises a case arranged within the cashbox, a sliding block movably arranged at an upper side of the case, a swing arm pivotally arranged in the case, and a circuit board with a plurality of contacts. The swing arm has one end pivotally driven by the sliding block and a probe on another end. The sliding block is moved laterally by an inserted coin, and the probe is swung due to the lever action of the swing arm. The probe is selectively in contact with one of the contacts according to the sizes of the inserted coin.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: January 7, 2003
    Inventor: Jer-Ming Cheng
  • Patent number: 6501817
    Abstract: An improved integrated circuit area efficient redundancy multiplexer circuit technique provides similar functionality to conventional CMOS transmission, or “pass” gates while concomitantly reducing circuit complexity, the die area necessary to support redundant elements and complementary control signals in memory device ICs and undesired parasitic capacitance. The technique of the present invention effectuates this end by utilizing the on-chip boosted voltage levels (Vpp) which are generally available in integrated circuit memory devices to supply the voltage for the control signal applied to a single N-channel transistor pass gate instead of the conventional supply voltage level of Vcc. The Vpp voltage and circuit ground (“GND”) are then utilized as the logic “high” and “low” signal levels respectively. This use is made possible due to the fact that these control signals operate at a direct current (“DC”) level after device power-up.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: December 31, 2002
    Assignees: United Memories, Inc., Sony Corporation
    Inventors: Michael Parris, Kim Hardee
  • Patent number: 6501317
    Abstract: A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105, 107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: December 31, 2002
    Assignee: Elantec Semiconductor, Inc.
    Inventors: Xijian Lin, Barry Harvey, Alexander Fairgrieve
  • Patent number: 6501816
    Abstract: The present invention is a method and system for a fully programmable modulus pre-scaler. In one embodiment, the pre-scaler is a cascade of fully programmable divide-by-⅔ sections. A fully programmable divide-by-⅔ section includes a state machine and a control circuit. The state machine generates a modulus control output synchronously with a clock signal in response to a modulus control input and a programming signal. The state machine has a plurality of states corresponding to a ⅔ divider. The control circuit is coupled to the state machine to generate the programming signal to the state machine in response to a programming word for a frequency divider.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: December 31, 2002
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Konstantin Kouznetsov, Daniel Linebarger
  • Patent number: 6496556
    Abstract: A PLL system (200) includes a clock sequence generator (190). Clock sequence generator (190) provides a clock that steps down from a fast frequency through several steps to a frequency of zero. This step-down non-linear digression of frequencies causes a counter (110) driving a tank circuit of a self-calibrating VCO to achieve lock at an extremely rapid rate. The PFD (150) generates an analog signal based on the phase and frequency relationship of the reference and feedback clock signals. The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit (120) and the signals UP and DOWN are supplied to the counter (110). The counter (110) provides a count value that controls the resonant frequency generated by the tank circuit. The convergence speed of the PLL system (200) is accelerated by the effects of the step-down clock provided by the clock sequence generator (190).
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: December 17, 2002
    Assignee: Motorola, Inc.
    Inventors: Karl J. Huehne, Klaas Wortel, Luis J. Briones
  • Patent number: 6490332
    Abstract: A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage a selected number of stages ahead in the chain and to the disable input of a stage a selected number of stages behind in the chain.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: December 3, 2002
    Assignee: Cirrus Logic, Inc.
    Inventor: Shyam S Somayajula
  • Patent number: 6483888
    Abstract: A clock divider circuit receives a first clock signal and frequency divides the first clock signal to generate a second clock signal. The first and second clocks are inputs to multiplexer (MUX) that selects one of the clocks as the MUX output based on the state of a MUX control signal. The MUX output is combined with a latched Freeze clock signal in an AND gate to generate a clock output signal. The state of Bypass logic signal determines which clock signal is selected as the clock output signal. The Bypass logic signal is received in a latch circuit which latches the Bypass logic signal in two series latches one latch latching on the positive edge and one on the negative edge of the MUX output. The output of the second latch is latched in a third latch on when a NOR logic gate signals the first and second clock are concurrently at a logic zero assuring that the MUX output is changed only when both clocks are low. The clock output signal is gated with the latched Freeze clock signal in the AND logic gate.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: November 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Gary D. Carpenter, Hung C. Ngo, Kevin J. Nowka
  • Patent number: 6483889
    Abstract: A shift register circuit is provided that is adaptive for reducing a swing width of a clock voltage. In the shift register, a plurality of stages, one for each scanning line, generate first driving signals in response to first and second clock signals. A level shifter is connected between each the stages and its respective scanning line to receive the first driving signal, to thereby apply a second driving signal having a larger swing width than the first driving signal to the scanning line.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: November 19, 2002
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Byeong Koo Kim, Soon Kwang Hong, Ju Cheon Yeo
  • Patent number: 6483887
    Abstract: A timer control circuit includes timers that perform count operations. A signal selection circuit selectively passes underflow signals supplied from the timers, based on control signals. A flip-flop is supplied with an output of the signal selection circuit section as a toggle signal.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: November 19, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Miyake, Kazuyuki Iwaguro
  • Patent number: 6473484
    Abstract: A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each element within a complete counting cycle. The invention extends to software or microcontroller implemented methods for counting, including encoding and decoding applications.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: October 29, 2002
    Assignee: Microchip Technology Incorporated
    Inventor: Robert P. Mather
  • Patent number: 6473483
    Abstract: The pedometer having improved accuracy by being calibrated to actual user stride lengths and stride rates, and being recalibrated as necessary based on subsequent actual stride rates and lengths. The pedometer can also interact with a heart monitoring device.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: October 29, 2002
    Inventor: Nathan Pyles
  • Patent number: 6473485
    Abstract: A leakage current compensation system and method is disclosed that reduces frequency spurs and phase offset in a frequency synthesizer. The leakage current is determined based on the phase offset of the frequency synthesizer relative to a reference clock. A leakage current compensation circuit provides a leakage current compensation signal to the frequency synthesizer at the loop filter terminals to minimize the phase offset.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: October 29, 2002
    Assignee: Micrel, Incorporated
    Inventor: Francisco Fernandez-Texon
  • Patent number: 6470063
    Abstract: Method and device to update a data count in a data transfer operation in which a data counter generates an intermediate count value in accordance with a first amount of data to be transferred to a storage media; and an augmenter augments the intermediate count value by a specified count value in accordance with data to be transferred to the storage media in addition to the first amount of data, wherein the updated count value is loaded into the data counter such that the intermediate count value becomes equal to the updated count value during the data transfer operation.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: October 22, 2002
    Assignee: Oak Technology, Inc.
    Inventor: Bee-Bee Liew
  • Patent number: 6470064
    Abstract: A synchronous counter, the inventive counter is synchronized to a clock, e.g., a master clock of an FPGA, and includes a first counter that increments in response to the master clock, a resynchronizer that receives counter bits from the first counter and, when appropriate, generates an increment signal, and a second counter, clocked by the master clock, that increments in response to the increment signal. In a preferred embodiment, the resynchronizer is an n bit AND gate (where the first counter is an n-bit counter) that ANDs at least selected ones of the counter bits and a latch, e.g., a flip-flop, that latches the output of the AND gate. Thus, small counter chains are linked together using flip-flops clocked at the master clock rate, i.e., the same rate as the counter chains, to form a counter chain of any length that will function at the master clock rate.
    Type: Grant
    Filed: October 8, 2001
    Date of Patent: October 22, 2002
    Assignee: Raytheon Company
    Inventor: Michael K. Carpenter
  • Patent number: 6462614
    Abstract: An electrothermal integrator and audio frequency filter utilizing an electrothermal structure fabricated by way of a micro-machining process. An electrothermal structure is a structure in which there is thermal interaction between its electrical components. It is possible to implement an audio frequency filter by properly integrating electrothermal structures fabricated by micro-machining technology and electrical circuitry, because thermal response is generally slower than electrical response. It is possible to implement a variety of filters by way of forming a Gm-C integrator utilizing an electrothermal structure and using this basic block of Gm-C integrator in general circuitry to form filters.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: October 8, 2002
    Assignee: Korea Advanced Institute of Science & Technology
    Inventors: Euisik Yoon, Kwang Hyun Lee, Hyung Kew Lee