Abstract: A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second input terminal coupled to receive a bit being shifted out of the shift register. The circuit further includes a sequential logic device having an input terminal coupled to an output terminal of the 2-input logic gate, an output terminal that provides the function, and a control terminal coupled to receive a control signal for resetting the sequential logic device. In one embodiment, the 2-input logic gate is an exclusive OR gate, and the sequential logic device is a toggle flip-flop. In this embodiment, the function is a logical exclusive OR of the consecutive bits in the shift register. The function is implemented by initializing an output signal of the sequential logic device when the consecutive bits of the shift register have a predetermined value.

Abstract: An event counter circuit including an input signal coupled to a frequency divider circuit that can be cleared by an external signal, a multiplexer coupled to the divider circuit driven by an output edge and its inverse, and a counter circuit coupled to the multiplexer driven by outputs of the multiplexer.

Abstract: Oscillator control circuitry for a phase lock loop, including phase detection circuitry, control signal generator circuitry, bias control circuitry and charge pump circuitry. The control signal generator circuitry introduces specific and distinct time delays to the phase signals from the phase detection circuitry representing the phase difference between the reference and oscillator output signals. These time delays cause the bias control circuitry to enable and disable the output charge pump circuitry slightly before and after, respectively, those time intervals during which an output source (“pump up”) or sink (“pump down”) current is needed to drive the oscillator via the loop filter. This produces charge pump circuitry output signals with significantly faster rise and fall times and shorter pulse widths, thereby resulting in a charge pump output signal with higher SNR and reduced spurious signal energy.

Abstract: A watchdog timer includes an instruction decoder, a delay circuit and a counter. The instruction decoder decodes a watchdog timer initialization instruction regularly executed to generate an instruction pulse for initializing the count of the counter. The delay circuit delays the rising edge of the instruction pulse, and supplies the delayed instruction pulse to the counter as a signal for initializing the count. The delay circuit prevents the pulse signal from being supplied to the counter when the operation frequency of the microcomputer is high or when the supply voltage to the microcomputer is low, so that the count of the counter overflows, and the overflow signal causes the microcomputer to be reset. This makes it possible to reset the microcomputer before it runs away, thereby solving a problem of a conventional watchdog timer in that the microcomputer can produce, if it runs away, an unexpected signal from its port before it is reset, and hence can impair the security of the system.

Abstract: A dual-modulus digital prescaler circuit having an extended period in which responses to a divider control indicating a possible modulus change must be made, such extended period permitting higher speed operation while suffering no penalty in manufacturing cost or increased power use. In embodiments comprising a dual modulus divider, a fixed-modulus divider and interconnected control logic, dual modulus divider state transitions giving rise to incrementing of fixed-modulus divider states are selected to be independent of short-term instabilities in divider control inputs. Identified critical state transitions associated with output signals from the dual modulus divider are constrained to occur at times prior to periods of insensitivity to stability of the dual-modulus control signal. Thus, timing of such output signals is determined so that there will be following time interval sufficient to provide desired stability of the modulus control signal for the next divide cycle.

Abstract: In this invention compare circuitry is integrated into a serial shift register which can detect a bit pattern of any length with only the delay of three circuits being added to the shift of the last bit in the bit pattern. The circuitry is connected to operate either is a shift register or as a comparator for an N element bit pattern. Between adjacent registers in the shift register is a MUX used to select compare or shift register operation. An exclusive NOR circuit performs the compare between bits of the serial bit stream and reference bits of the pattern to be protected. An AND circuit accumulates the compare of a particular stage with the compare with the preceding stage. In the last stage the AND circuit provide an accumulated compare result of the preceding number of bit equaling in length the length of the bit pattern for which the compare is being performed.

Abstract: A filter on which living bacteria are captured is processed with an extraction reagent and a luminescence reagent. The state of luminescence of the filter is photographed by a television camera 1 including an optical system and an image acquisition means such as a charge coupled device. The number of luminous points is counted from data for the image of the luminous points of fluorescence originating in microbes through an image processing device 3 and a data-analyzing device 4. The result of the count is shown on a display 5. In the analysis of the data, when there exists a first luminous point adjacent to a second luminous point, the first and second luminous points are grouped and counted as one luminous point. A process for eliminating the effect of the diffusion of light from a luminous point of great luminance is performed.

Abstract: An assembly for generating a consecutive count includes an n-stage binary counter (24) incrementable by counting pulses in successive cycles and an EEPROM (10) in which an item of information representing the count achieved in each case is stored in the pauses between the cycles. The EEPROM (10) comprises n+1 memory cells. A control circuit (36) is provided causing the contents of the n−1 stages of the binary counter (24) assigned to the most-significant bits to be stored in the n−1 first memory cells of the EEPROM (10) and the contents of the nth or (n+1)th memory cell is changed in alternate cycles.

Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

Abstract: An apparatus that performs a left shift operation includes a shifter unit that contains the value to be shifted, a flag having an input coupled to the left-most bit of the shifter unit for receiving sign bit information for the value to be shifted, an overflow detector having inputs coupled to the shifter unit and the flag for determining the existence of an overflow condition, and a shift counter having outputs coupled to the shifter unit and the overflow detector.

Abstract: The present invention is directed to a pill-counting machine and method of counting pills that uses a rotatable first pill rotor having a plurality of holes, a second pill rotor having a single orifice and a rotatable third pill rotor having a plurality of chambers.

Abstract: A counting apparatus is disclosed, having a resettable counter, for counting the number of times a mold closes. The counting apparatus includes a body that is mountable to a mold block section, an electronic counting mechanism connected to the body, and a reset mechanism connected to the body that resets the counting mechanism to zero or some other settable number. Additionally, the counting mechanism includes a sensor, a triggering mechanism, and a counter display. The sensor detects when the mold has been closed and then communicates such with the triggering mechanism. The triggering mechanism then triggers the counter display to increase or decrease by the number of units associated with the closing of the mold.

Abstract: An object feeding, counting, and dispensing device is provided which includes a feeding funnel having a pathway having an entrance into which discrete objects are provided and an exit, an object sensing system at the exit of the pathway, a dispensing funnel having an upper opening into which the objects are gravity fed after passing through the object sensing system and a relatively smaller lower opening, a vibration system which substantially silently vibrates the dispensing funnel in a horizontal plane, and preferably not a vertical plane, and a display indicating the number of object counted. According to a preferred aspect of the invention, the vibration system includes a weight, a motor coupled to the dispensing funnel which eccentrically rotates the weight through XY plane such that rotation of the weight creates forces in X and Y directions, and a system which cancels the force in one of the X and Y directions.

Abstract: A method and system for detecting a presence of more than one item at a point along a conveyance path, comprising steps of (A) generating a light beam and directing the beam through the path such that a presence of the item will cause the beam to be attenuated; (B) detecting the beam after it is attenuated by the presence of the item; and (C) determining from the amount of attenuation how many items are simultaneously present. In the preferred embodiment the item is an item of currency, and the step of generating a light beam includes a step of operating an optical source, such as an LED or a laser, to generate a beam having a wavelength in the range of about 400 nm to about 1 micrometer or longer.

Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.

Abstract: An apparatus for counting flexible flat objects, such as printed products, which are conveyed in an overlapping formation. A detection device counts the objects as they are being conveyed, and comprises an insertion element which is moved in the direction of conveyance at a speed greater than the conveying speed of the objects so as to catch up with an object and interact with an end section of the object, and a detection element which emits a signal to a counter when the insertion element interacts with an end section of an object.

Abstract: A frequency correction circuit includes a temperature sensor (100) disposed to measure temperature and produce temperature signals representing sensed temperatures. A data supplier (110) stores information items, receives digital input signals representing and produces a digital output information signal representing an item selected in accordance with the digital input signal. A control circuit (120) receives the temperature signals and receives the digital output information signal. The control circuit (120) produces control signals based on the temperature signals. A clock circuit (150) is disposed to generate a reference frequency signal. A digital synthesizer (130) receives the reference frequency signal and the control signals. The digital synthesizer produces an output frequency signal as directed by the control signals received from the control circuit (120).

Abstract: Certain events occurring throughout a microprocessor chip are monitored by a counter system (1) containing a number of digital electronic counters (3, 5, 7 & 9) consolidated at a single location on the processor chip. Those events are communicated to the counter system via electrical leads extending to those functional units in the processor responsible for signaling an event occurrence. Under program control, each counter can be selectively connected (11, 13, 15 & 17) to a selected one of the various functional event producing units. By means of selection logic (19, 21, 23 & 25) separate events originating from multiple functional units may be logically combined, whereby the event counted is a Boolean logic combination of multiple underlying events.

Abstract: A clock generator circuit includes an oscillation circuit which generates a first clock signal, a first timer which counts the first clock signal, a ring oscillator which generates a second clock signal, a second timer which counts the second clock signal, and a third timer that generates a third clock signal which is the output clock signal.

Abstract: A pedometer determines that the user does not wear the pedometer when the current number of steps is not more than a prescribed set value, not to employ the data of the current number of steps on the day the user does not wear the pedometer for calculating an average number of steps. If the current number of steps is in excess of the set value, the pedometer determines that the user wears the pedometer for adding the current number of steps to the total number of steps, adding 1 to the number of days and dividing the total number of steps by the number of days for calculating an average number of steps per day. Consequently, a pedometer having a function of displaying the average number of steps per day, which can not only maintain correctness of the average number of steps but also keep the user interested in exercise even if the user forgets wearing the pedometer, can be provided.