Abstract: A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector.

Abstract: A fractional divider divides an input frequency of a first signal (Fi) by a rational, non-integral number, which rational number is greater than one and, when written as vulgar fraction, can only be written with a denominator not equal to one. The device comprises a number of series connected delay elements (a, b, c, . . . , R). Each of the delay elements (a, b, c, . . . , R) adds a predetermined delay to the signal of a previous delay element (a, b, . . . , R-1). The first signal (Fi) is applied to the first delay element (a). The delay added again and again per delay element equals the period of the first signal (Fi) divided by the denominator of the vulgar fraction of the rational number. A counter (2) counts pulses of the first signal (Fi), which counting takes place modulo the numerator of the rational number and in steps of the denominator of the rational number. A decoder circuit (6) decodes counting scores of the counter (2), which appear successively at an output (6a, . . .

Abstract: A system and a method are characterized in that the method of detection can be configured by varying a size and/or a position of a time slot to be taken into consideration for the detection and/or by varying relevant bits of the counts to be compared. This makes it possible to individually adapt the detection method to various or varying requirements at any time and with a minimum of expenditure required.

Abstract: Disclosed is a method and apparatus for shifting data from registers. Bits from N registers are shifted as input to a first set of M multiplexors. Control signals are sent into each of the first set of M multiplexors to select bits inputted from one of the registers. The selected bits are outputted to each of a second set of M multiplexors. Control signals are then sent into each of the second set of M multiplexors to select bits inputted from each of the first set of multiplexors.

Abstract: A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter. In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of N cycles per second and output a second clock signal having a frequency of M cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N−M. The look-ahead circuit determines for a present clock cycle the rollover point for a preceding clock cycle. The look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.

Abstract: A system and method are presented for providing a multi-stage counter. In one embodiment, a signal propagates from the most significant bit of the counter to the least significant bit of the counter that indicates that all “more significant” stages of the counter have reached a limit value (e.g., all 1's). Use of this propagating signal means that only the first (or first couple) stages of the counter are time critical, while the remainder are less so. The described counter may have a modular design and may result in lower power consumption.

Abstract: A low voltage reset circuit device without being influenced by temperature and manufacturing process is formed by a first low voltage reset circuit using an energy gap circuit to generate a reference voltage, and a second low voltage reset circuit using a threshold voltage of a MOS transistor as a reference voltage. The first low voltage reset circuit is used to provide an accurate low voltage reset property,. while the circuit only works as VDD>1.2V. When VDD<1.2V, the second low voltage reset circuit still works normally for providing the desired reset signal thereby covering the low VDD voltage range.

Abstract: The rotation of a pneumatic tire is monitored by a self powered tire revolution counter. A piezoelectric (“piezol”) element is mounted in the tire in a manner so as to be subjected to periodic mechanical stresses as the tire rotates and to provide periodic pulses in response thereto. The output of the piezo element is utilized by revolution counting circuitry to count rotations of the tire, as well as by power circuitry to power the revolution counting circuitry.

Abstract: A low power, low area shift register permits control over delay by dividing the shift register cells into a plurality of segments that are serially connected. A first selector provides data from a shift register input selectively to an input of one of the segments. A second selector provides data from an input or output of a selected cell of one segment of shift register cells to a shift register output.

Abstract: The pedometer having improved accuracy by calculating actual stride lengths of a user based on relative stride rates. The pedometer includes a waist or leg mounted stride counter, a transmitter for transmitting data to a wrist-mounted display unit, and a data processor for calculating necessary base units and actual stride rates and lengths. The pedometer can also interact with a heart monitoring device.

Abstract: An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register. A plurality of pre-load flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop units and multiplexers. The PLFF circuits hold two initial LFSR sequence values. A load enable signal to the PLFF multiplexers and LFSR multiplexers is high for two input clock cycles. The present invention is capable of operating at high frequencies due to a shortened critical timing path.

Abstract: The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry fed into a counter so that any bit (or bits) of the counter may be masked. A masked bit of a maskable counter system and method is utilized to facilitate user programmable control of multiple configurations in a memory. A maskable counter system comprises a mask register (e.g., a D flip flop), a counter (e.g., a D flip flop), and a masking coordination circuit. The masking coordination circuit permits a carry in signal, a carry out signal, and a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents the counter output bit signal from changing if the mask bit is asserted.

Abstract: The present invention provides an automatic identification level control circuit, an identification level control method, an automatic identification phase control circuit, an identification phase control method, and an optical receiver, capable of stably setting an optimal identification level or identification phase. An automatic identification level control circuit of the present invention includes a coupling capacitor, an identification circuit, a level fluctuation detection circuit, an identification voltage control circuit, and a low-pass filter. The identification circuit includes limiter amplifiers and flip flops. The level fluctuation detection circuit includes exclusive OR circuits.

Abstract: A method for counting substantially uniformly sized objects includes the steps of obtaining an image of substantially uniformly sized objects; analyzing the image to determine total object area in the image and average object size of the objects; and determining a count of the objects from the total object area and the average object size.

Abstract: A score counter for sensing route of basketball shots includes a pair of photoelectric sensors installed at respective positions below an inner rim of a basket hoop to detect basketball valid shots. Such an arrangement overcomes basket net interference to the photoelectric sensors to avoid malfunctions and is capable of discriminating the correct route after a basketball is thrown into the basket hoop.

Abstract: A dual-modulus prescaler for a RF frequency synthesizer, which may operate in a high speed and reduce energy consumption with use of a selective latching technique includes a first frequency-dividing circuit for being synchronized to the clock signal to generate a latch control signal, latching the clock signal at a leading edge of the generated latch control signal, changing the frequency-dividing mode from a first frequency-dividing mode to a second frequency-dividing mode when latching the clock signal, and frequency-dividing and outputting the clock signal; a second frequency-dividing circuit for frequency-dividing the frequency divided signal from the first frequency-dividing circuit at a predetermined frequency-dividing ratio and outputting a plurality of frequency divided signals; and a logic operation circuit for logically operating a plurality of the frequency divided signals and the mode control signal to control the frequency-dividing mode of the first frequency-dividing circuit.

Abstract: A clock divider circuit having a fifty per cent duty cycle and multiple integer ratios for dividing an input clock signal. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives. The first clock signal may be divided by an even or an odd integer ratio, or may be divided by an integer ratio (e.g. 2.

Abstract: A frequency divider and method for dividing a clock signal. The frequency divider including a first configurable signal generator, a second configurable signal generator, a data source coupled to the signal generators providing configuration data based on instructions received at an instruction port, a sequencer generating the instructions coupled between the signal generators and the data source and passing the instructions to the instruction port of the data source, and combining logic coupled to the outputs of the signal generators to produce the reduced frequency signal.

Abstract: A dispensing device for dispensing powder foods or liquids has a scoop for containing the powder or liquid, and levelling means for levelling off the scoop contents, wherein the levelling means co-operates with a counter such that operation of the levelling means is adapted to advance the counter, the counter being characterised in that the counter may be reset to zero in a single step process.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.