Abstract: An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit or externally by one or more sources external to the integrated circuit. The embedded counter assembly utilizes a reference clock signal having known characteristics, and measures the frequency of an unknown clock signal based upon the reference clock signal. The embedded counter assembly is capable of measuring the frequency of internal clock signals that are otherwise inaccessible via external output pins.

Abstract: A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.

Abstract: An electronic pedometer to accurately measure stride length of a walker includes a processing unit with an ultrasonic sound wave receiver attached to one foot and an ultrasonic sound wave generator attached to the other foot. Pressure sensitive switches close when each foot makes a step, providing signals to the processing unit to record the number of strides. The processing unit computes stride length by calculating distances using the ultrasonic sound waves.

Abstract: A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset signal which holds all configuration registers in a reset condition until the frequency multiplier achieves a locked state. The configuration registers are dependent upon the internal clock signal generated by the frequency multiplier for proper operation. By causing the configuration registers to renew operation only after the stable frequency multiplier operation the danger of corrupting the information in the configuration registers is minimized.

Abstract: An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback shift register of the present invention may be used as a clock divider circuit.

Abstract: An Address Compare Circuit (1) allows for a large compare function at high speed due to its unique self-timed evaluation clock and bit compare circuits. The address compare circuit can reliably self-time off of the input data which insures proper compare timing with respect to the arrival of two address busses being compared. The HIT evaluation clock is generated by a circuit that has additional control inputs to increase the arrival times of input data, resulting in a greater operating window. This circuit provides a way to generate a very accurate internal HIT evaluation clock; therefore, the compare circuit reduces the extra setup time needed to guarantee all address data bits are valid. Furthermore, the HIT evaluation clock can be delayed to increase the arrival times of input data, resulting in a greater operating window.

Abstract: A conventional up/down Gray code counter has both a logic circuit section for up counting and a logic circuit section for down counting, and thus has a large circuit scale. To overcome this inconvenience, an up/down Gray code counter of the invention has a one-way Gray code counter that can count only in one, up or down, direction and a highest bit selecting circuit that receives the highest bit of the data output from the one-way Gray code counter and that then outputs the bit selectively either intact or after inverting it.

Abstract: A shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output terminal. The input terminal of one stage receives the signal delivered from an input terminal of the shift register or from the output terminal of the previous stage. The signal output at the output terminal of one stage is passed to the input terminal of the subsequent stage or to an output terminal of the shift register. Each stage receives an initial state level from one of the clock input terminals. The initial state level is used to initialize the state of each stage.

Abstract: A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider.

Abstract: A system and method is presented for dividing a reference clock frequency by any real number. The invention allows for a real number divisor that could have any desired degree of precision. Additionally, the invention seeks to minimize hardware complexity in realizing such a reference-clock frequency divider. In one particular embodiment of the invention, a system and method is presented, wherein the real number divisor is a real number having a repeating decimal (i.e., the real number may be represented by a fraction).

Abstract: A multi-modulus prescaler with a terminal count request input, which when set causes the prescaler to produce an output pulse with edges synchronous with the input clock. The prescaler is driven by a control circuit which produces a terminal count request output which enables the prescaler to generate a terminal count output pulse whose active edge, irrespective of the divide ratio, is always a fixed number of input clock cycles before or after the end of the prescaler control cycle.

Abstract: The present invention discloses a glitch-free frequency dividing circuit, comprising: a frequency dividing module, dividing the frequency of a reference pulse according to the divisor, outputting a frequency divided output pulse and receiving a control signal such that the state of the frequency divided output pulse is maintained the same when the control signal is enabled; and a latch module, detecting the state of the frequency divided output pulse after a divisor switching signal is received, enabling the control signal when the frequency divided output pulse is as pre-determined, switching the divisor when the frequency divided output pulse is as pre-determined and disabling the control signal after the divisor is switched; whereby the generation of the glitch is prevented during the switching of the divisor.

Abstract: To divide a clock signal, a clock pulse counter counting clock pulses of the clock signal is in each case alternately reset after passing through different count differences. In this process, a first signal and a second signal is formed, the logic state of which is in each case changed with the presence of a first or, respectively, second predetermined count of the clock pulse counter by a rising or, respectively, falling clock signal edge. A divided output clock signal is then generated by a logical operation on the first and the second signal.

Abstract: A counter unit counts discrete articles that are within a predetermined size range into lots having a predetermined number of articles. The counter unit includes (1) a first conveyor that delivers a flow of articles separated at discrete intervals; and (2) at least one bin positioned to receive articles from the conveyor. The at least one bin has at least first and second outlet gates for emptying articles into separate respective first and second locations. A detector unit detects and maintains a count of articles that are received in the at least one bin and fall within said predetermined size range. The detector unit generates an out-of-size signal when an article received in the at least one bin falls outside said predetermined size range. A control unit causes the first outlet gate to open when the count of articles is equal to said predetermined number and causes the second outlet gate to open in response to receipt of an out-of-size signal.

Abstract: A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal, i.e., by presetting the state of each of the bit combinations and outputting a next required value.

Abstract: An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of “pre-load” flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.

Abstract: An improved DDLL containing a majority filter counter circuit is disclosed. The majority filter counter circuit is located between the phase detector and the shift register of the DDLL. The majority filter counter circuit receives shifting commands from the phase detector and filters the shift commands from reaching the shift register until a predetermined number (e.g., 16) have been received from the phase detector before transmitting a shift command (either shift right or shift left) to the shift register. Once the shift register receives the shift command, the shift register directs the delay line to shift by one tap in either a shift right or a shift left direction depending upon the phase relationship between CLKIn and CLKOut. By waiting for e.g., 16 shift commands, the majority filter counter circuit ensures that a premature shift command is not delivered to the shift register in the case of a noise event.

Abstract: A frequency multiplier circuit and a controlling method thereof, which measures a period of a waveform by counting cycles of a fixed frequency timing signal, and reproduces the period by adding a number of prefixed length subperiods of the fixed frequency to the cycle count, making it as equal as possible to the period, so to minimize the reproduction error.

Abstract: A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reaches a first predetermined amount of time, where the first predetermined amount of time is related to a parameter of the second circuit. The second timer may produce a second output in the given state if the first timer does not produce the first output in the given state when the duration of the pulse reaches a second predetermined amount of time. The one or more logic gates may have an output that is the same as the pulse unless and until the output of the first timer or the second timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state.

Abstract: A command buffer for use in packetized DRAM includes a four stage shift register for shifting for sequentially storing four 10-bit command words. The shift register combines the four 10-bit command words into a single 40-bit command word and transfer the 40-bit command word to a storage register for processing by the DRAM. The shift register may then continue to receive and store subsequent 10-bit command words. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device. Specifically, a portion of the 40-bit command word from the storage register is compared to identifying data stored in an identifying latch. In the event of a match, a chip select signal is generated to cause the memory device to perform the function corresponding to other portions of the 40-bit command word.