Abstract: A semiconductor device and a method of manufacturing the same are provided. The device includes insulating patterns and conductive patterns stacked alternately, a channel layer formed through the insulating patterns and the conductive patterns, a tunnel insulating layer formed to surround sidewalls of the channel layer, and a charge storage layer formed to surround the tunnel insulating layer. An interfacial surface of the tunnel insulating layer in contact with the charge storage layer includes a thermal oxide layer.

Abstract: An anode region 106 is formed on a bottom portion of a trench 105 in which a gate electrode 108 is formed or in a drift region 102 immediately under the trench 105. A contact hole 110 is formed in the trench 105 at a depth reaching the anode region 106. A source electrode 112 is embedded in the contact hole 110 while interposing an inner wall insulating film 111 therebetween. The anode region 106 and the source electrode 112 are electrically connected to each other in a state of being insulated from the gate electrode 108 by the inner wall insulating film 111.

Abstract: A light-emitting-element mount substrate formed by relatively simple manufacturing steps, having a good heat release property, and having a high mechanical strength; and an LED device including the light-emitting-element mount substrate are provided. A substrate body of a light-emitting-element mount substrate is made of a low-resistance semiconductor (e.g., n-type silicon) substrate, and is divided into a first and second individual substrate bodies by an insulating layer. A first front-surface mounting electrode and a first external-connection electrode are formed on respective first and second major surfaces (e.g., front and back surfaces) of the first individual substrate body. A second front-surface mounting electrode and a second external-connection electrode are formed respective first and second major surfaces (e.g., front and back surfaces) of the second individual substrate body. The insulating layer has a shape different from a straight-line shape in plan view.

Abstract: A phosphor for light emitting device of an embodiment includes: a phosphor particle composed of at least one selected from an alkaline earth silicate phosphor, a lanthanum oxysulfide phosphor, and a zinc sulfide phosphor; and a surface treatment agent, provided to cover a surface of the phosphor particle, of at least one selected from a silane coupling agent and an acrylic emulsion. A luminance maintenance ratio of the phosphor represented by a formula: luminance B/luminance A×100(%), is 98% or more, wherein the luminance A is a luminance of the phosphor made to emit under a condition of temperature: 23° C., humidity: 40%, and the luminance B is a luminance of the phosphor made to emit under a condition of temperature: 23° C., humidity: 40% after leaving the phosphor under a condition of temperature: 60° C., humidity: 90% for 12 hours.

Abstract: A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses.

Abstract: In this method for producing a photoelectric conversion device: an i-type non-crystalline layer and an n-type non-crystalline layer comprising a non-crystalline semiconductor film are formed on the light-receiving surface of a semiconductor substrate; an i-type non-crystalline layer and an n-type non-crystalline layer comprising a non-crystalline semiconductor film are formed on the back surface of the semiconductor substrate; a protective layer is formed on the n-type non-crystalline layer; an insulating layer is formed on the n-type non-crystalline layer; and in the state where the top of the n-type non-crystalline layer is covered by the protective layer, patterning is performed by eliminating a portion of the i-type non-crystalline layer, the n-type non-crystalline layer, and the insulating layer.

Abstract: To satisfy both suppression of rise in contact resistance and improvement of breakdown voltage near the end part of a trench part. The trench part GT is provided between a source offset region and a drain offset region at least in plan view in a semiconductor layer, and is provided in a source-drain direction from the source offset region toward the drain offset region in plan view. A gate insulating film GI covers the side surface and the bottom surface of the trench part GT. A gate electrode is provided in the trench part at least in plan view, and contacts the gate insulating film GI. A contact GC contacts the gate electrode GE. The contact GC is disposed, shifted in a first direction perpendicular to the source-drain direction relative to the centerline in the trench part GT extending in the source-drain direction in plan view, and is provided in the trench part GT in plan view.

Abstract: A light emitting device (100) includes a base member (101), electrically conductive members (102a, 102b) disposed on the base member (101), a light emitting element (104) mounted on the electrically conductive members (102a, 102b), an insulating filler (114) covering at least a portion of surfaces of the electrically conductive members (102a, 102b) where the light emitting element (104) is not mounted, and a light transmissive member (108) covering the light emitting element (104).

Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: An oxide semiconductor includes a first material including at least one selected from the group consisting of zinc (Zn) and tin (Sn), and a second material, where a value acquired by subtracting an electronegativity difference value between the second material and oxygen (O) from the electronegativity difference value between the first material and oxygen (O) is less than about 1.3.

Abstract: A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer.

Abstract: A nitride semiconductor light-emitting element includes: n-side and p-side electrodes; n-type and p-type nitride semiconductor layers; and an active layer arranged between the n- and p-type nitride semiconductor layers. The p-type nitride semiconductor layer has a projection having a height of 30 nm to 50 nm. The projection is formed of a p-type nitride semiconductor including magnesium and silicon. The p-type nitride semiconductor has a silicon concentration of 1.0×1017 cm?3 to 6.0×1017 cm?3. The projection projects from the active layer toward the p-side electrode. On a plan view of the nitride semiconductor light-emitting element, the p-side electrode overlaps with the projection. The projection includes a dislocation. The projection is surrounded with a flat surface which is formed of the p-type nitride semiconductor. And the projection has a higher dislocation density than the flat surface.

Abstract: An organic light-emitting diode includes a first electrode and a second electrode facing the first electrode; an emission layer between the first electrode and the second electrode; a hole transport layer between the first electrode and the emission layer and includes a first hole transport layer, a second hole transport layer, and a buffer layer between the first hole transport layer and the second hole transport layer; and an electron transport layer between the emission layer and the second electrode, wherein the buffer layer and the electron transport layer each include a mixture of an electron-transporting organometallic compound and an electron-transporting organic compound.

Abstract: An elementary image acquisition or display device, including a focusing structure with microlenses, each microlens being shaped to focus incident light beams towards a substrate while avoiding intermediate conductive tracks and vias.

Abstract: A first first-conductivity-type impurity region (4) is provided in an upper portion of a semiconductor layer (102) around a trench (12). A gate electrode (8) is provided on a sidewall surface of the trench (12), and on the semiconductor layer (102) around the trench (12) with a gate insulating film (11) interposed therebetween. A second-conductivity-type impurity region (50) and a second first-conductivity-type impurity region (51) are interposed between a portion of the gate electrode (8) around the trench (12) and the first first-conductivity-type impurity region (4) sequentially on the first first-conductivity-type impurity region (4).

Abstract: A method for forming germanium tin layers and the resulting embodiments are described. A germanium precursor and a tin precursor are provided to a chamber, and an epitaxial layer of germanium tin is formed on the substrate. The germanium tin layer is selectively deposited on the semiconductor regions of the substrate and can include thickness regions of varying tin and dopant concentrations. The germanium tin layer can be selectively deposited by either alternating or concurrent flow of a halide gas to etch the surface of the substrate.

Abstract: A method of fabricating a pressure sensor includes performing a chemical vapor deposition (CVD) process to deposit a first sacrificial layer having a first thickness onto a substrate. A portion of the first sacrificial layer is then removed down to the substrate to form a central region of bare silicon. One of a thermal oxidation process and an atomic layer deposition process is then performed to form a second sacrificial layer on the substrate having a second thickness in the central region that is less than the first thickness. A cap layer is then deposited over the first and second sacrificial layers.

Abstract: A display panel includes a substrate, a TFT device, a patterned dielectric layer, a patterned metal layer and a bridge line. The TFT device is disposed in a display region. The patterned dielectric layer includes an ILD layer disposed over the TFT device, and a sealant stage disposed in a peripheral region. The patterned metal layer includes a signal line disposed on the ILD layer, and a first connecting line and a second connecting line. The first connecting line is disposed in an inner side of the sealant stage facing the display region, and the first connecting line is electrically connected to the signal line. The second connecting line is disposed in an outer side of the sealant stage opposite to the display region. The bridge line is disposed under the sealant stage, and the first connecting line and the second connecting line are electrically connected through the bridge line.

Abstract: A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both n-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

Abstract: An organic EL element comprises: an anode; a cathode; a functional layer including at least a light-emitting layer; a hole injection layer disposed between the anode and the functional layer; and a bank. The hole injection layer contains tungsten oxide. Tungsten atoms constituting the tungsten oxide include both tungsten atoms with a valence of six and tungsten atoms with a valence less than six. The hole injection layer includes a crystal of the tungsten oxide. A particle diameter of the crystal is on an order of nanometers. The hole injection layer has a recessed portion whose inner side surface has an upper edge that is one of (i) aligned with part of a lower edge of the bank, the part being in contact with the light-emitting layer, and (ii) in contact with a bottom surface of the bank.