Patents Examined by Wasiul Haider
  • Patent number: 10910405
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
  • Patent number: 10903458
    Abstract: An optoelectronic assembly comprising an optoelectronic component, which comprises a specularly reflective surface and comprising a radiation cooler in direct physical contact with the optoelectronic component. The radiation cooler is arranged above the specularly reflective surface.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 26, 2021
    Assignee: PICTIVA DISPLAYS INTERNATIONAL LIMITED
    Inventors: Dominik Pentlehner, Richard Baisl
  • Patent number: 10896970
    Abstract: A process of forming a field effect transistor (FET) of a type of high electron mobility transistor (HEMT) reducing damages caused in a semiconductor layer is disclosed. The process carries out steps of: (a) depositing an insulating film on a semiconductor stack; (b) depositing a conductive film on the insulating film; (c) forming an opening in the conductive film and the insulating film by a dry-etching using ions of reactive gas to expose a surface of the semiconductor stack; and (d) forming a gate electrode to be in contact with the surface of the semiconductor stack through the opening, the gate electrode filling the opening in the conductive film and the insulating film.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 19, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Tadashi Watanabe, Hajime Matsuda
  • Patent number: 10886214
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Patent number: 10886203
    Abstract: A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: January 5, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Katsuhiro Iwai
  • Patent number: 10879361
    Abstract: A method for manufacturing a semiconductor structure including following steps is provided. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 29, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chen-Wei Pan
  • Patent number: 10879115
    Abstract: A method includes forming a first metal into a first trench in a dielectric layer, performing a thermal treatment to the first metal such that an average grain size of the first metal is increased, and performing a first chemical mechanical polish (CMP) process to the first metal after the performing the thermal treatment.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Han Lee, Shih-Kang Fu, Meng-Pei Lu, Shau-Lin Shue
  • Patent number: 10879426
    Abstract: A mount (10) and an optoelectronic component (100) with the mount (10) are provided, wherein the mount (10) comprises a moulding (5), at least one through-contact (41, 42) and a plurality of reinforcing fibres (52), wherein the moulding (5) is formed from an electrically insulating moulding material (53), the through-contact (41, 42) is formed from an electrically conductive material, and the reinforcing fibres (52) produce a mechanical connection between the moulding (5) and the through-contact (41, 42) by the reinforcing fibres (52) being arranged in certain regions of the moulding (5) and arranged in certain regions of the through-contact (41, 42). A method for producing a mount or a component with such a mount is also provided.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: December 29, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Lutz Hoeppel, Matthias Sabathil, Norwin Von Malm
  • Patent number: 10867848
    Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
  • Patent number: 10865470
    Abstract: A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 15, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masashi Tsubuku
  • Patent number: 10867882
    Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
  • Patent number: 10854785
    Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. An n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second metallic contact layer can be located over a second portion of the n-type contact region, where the second metallic contact layer is formed of a reflective metallic material.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 1, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Maxim S. Shatalov, Mikhail Gaevski, Michael Shur
  • Patent number: 10854540
    Abstract: A packaged IC component having a semiconductor body and a printed circuit board. The semiconductor body includes a monolithically integrated circuit and at least two metal contact areas. The printed circuit board has a first and second region and a top and a bottom. At least two formed terminal contacts and two conductive traces are connected to the terminal contacts, and the terminal contacts are designed as contact holes passing through the printed circuit board, and are arranged in the first region of the printed circuit board. The two metal contact areas are connected to the conductive traces by bond wires, and the semiconductor body is implemented as a die. The die is arranged in the second region on the top of the printed circuit board, and the semiconductor body and the bond wires are completely covered with a potting compound on the top of the printed circuit board.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: December 1, 2020
    Assignee: TDK-Micronas GmbH
    Inventors: Joerg Franke, Thomas Leneke
  • Patent number: 10847482
    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Patent number: 10847415
    Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. The method additionally includes selectively recessing the gate electrode of the at least one gate stack against the spacer material, thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: November 24, 2020
    Assignee: IMEC vzw
    Inventors: Julien Ryckaert, Juergen Boemmels
  • Patent number: 10840233
    Abstract: A switch fabrication method can include forming a plurality of elements, and connecting the elements in series between a first terminal and a second terminal, such that the elements include a first end element connected to the first terminal and a second end element connected to the second terminal. Each element can have a parameter such that the elements have a distribution of parameter values that decreases from the first end element for at least half of the elements to a minimum parameter value corresponding to an element between the first end element and the second end element. The minimum parameter value can be less than the parameter value of the second end element, and the parameter value of the first end element can be greater than or equal to the parameter value of the second end element.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Yu Zhu, David Scott Whitefield, Ambarish Roy, Guillaume Alexandre Blin
  • Patent number: 10840360
    Abstract: A nanosheet transistor device having reduced access resistance is fabricated by recessing channel nanosheets and replacing the channel material with epitaxially grown doped extension regions. Sacrificial semiconductor layers between the channel nanosheets are selectively removed without damaging source/drain regions epitaxially grown on the extension regions. The sacrificial semiconductor layers are replaced by gate dielectric and gate metal layers.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10833165
    Abstract: In a semiconductor device being fabricated, a gate structure, a first source/drain (S/D) structure, and a second S/D structure are formed. A first spacer of a first dielectric material is formed between the gate structure and the first S/D structure. A second spacer is formed between the gate structure and the second S/D structure, such that a first gap is created within a second dielectric material of the second spacer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Son Nguyen, Chanro Park
  • Patent number: 10833253
    Abstract: A magnetoresistive random access memory device (MRAM) device is described. The MRAM device has a stack arrangement in which a tunnel barrier layer is formed over a magnetizable reference layer, a metal layer is formed over the tunnel barrier layer, a free layer of a magnetizable material is formed over the metal layer, and an oxide layer is formed over the free layer as a cap layer. The resulting MRAM device has a thin free layer that exhibits a low magnetic moment.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventor: Guohan Hu
  • Patent number: 10833192
    Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek