Patents Examined by Wasiul Haider
  • Patent number: 10825850
    Abstract: The present technology relates to an imaging element, an imaging device, and a manufacturing apparatus and a method that facilitate electric charge transfer. An imaging element of the present technology includes a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit. Also, an imaging device of the present technology includes: an imaging element including a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit; and an image processing unit that performs image processing on captured image data obtained by the imaging element.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 3, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Shinpei Fukuoka
  • Patent number: 10825939
    Abstract: Provided is a field shaping multi-well photomultiplier and method for fabrication thereof. The photomultiplier includes a field-shaping multi-well avalanche detector, including a lower insulator, an a-Se photoconductive layer and an upper insulator. The a-Se photoconductive layer is positioned between the lower insulator and the upper insulator. A light interaction region, an avalanche region, and a collection region are provided along a length of the photomultiplier, and the light interaction region and the collection region are positioned on opposite sides of the avalanche region.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: November 3, 2020
    Assignee: The Research Foundation for The State University of New York
    Inventors: Amirhossein Goldan, Wei Zhao
  • Patent number: 10825808
    Abstract: The semiconductor device includes a semiconductor layer having a main surface, a first semiconductor region of a first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a second semiconductor region of a second conductivity type formed in a surface layer portion of the first semiconductor region and forming a zener diode with the first semiconductor region, a third semiconductor region of the first conductivity type formed in the surface layer portion of the first semiconductor region separated from the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in a region between the second semiconductor region and the third semiconductor region in the surface layer portion of the first semiconductor region and having a second conductivity type impurity concentration less than a second conductivity type impurity concentration of the second semiconductor region, and an insulating layer formed on the main surface of the se
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 3, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Toshiyuki Kanaya, Tsuyoshi Hosono
  • Patent number: 10797058
    Abstract: The present disclosure provides example embodiments relating to conductive features, and methods of forming the conductive features, that have differing dimensions. In an embodiment, a structure includes a substrate, a dielectric layer over the substrate, and first and second conductive features through the dielectric layer to first and second source/drain regions, respectively, on the substrate. The first conductive feature has a first length along a longitudinal axis of the first conductive feature and a first width perpendicular to the first length. The second conductive feature has a second length along a longitudinal axis of the second conductive feature and a second width perpendicular to the second length. The longitudinal axis of the first conductive feature is aligned with the longitudinal axis of the second conductive feature. The first width is greater than the second width, and the first length is less than the second length.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10790296
    Abstract: A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takashi Yamaha, Katsuya Kato, Kazuto Watanabe, Hajime Yamamoto, Michiaki Sano, Koichi Ito, Ikue Yokomizo, Ryo Hiramatsu, Hiroshi Sasaki
  • Patent number: 10784194
    Abstract: Embedded resistors which have tunable resistive values located between interconnect levels are provided. The embedded resistors have a pillar structure, i.e., they have a height that is greater than their width, thus they occupy less real estate as compared with conventional planar resistors that are typically employed in BEOL technology.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli
  • Patent number: 10777650
    Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
  • Patent number: 10770340
    Abstract: The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: September 8, 2020
    Assignees: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD., HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventors: Yongxiang Wen, Shaohua Zhang, Yulei Jiang, Yanghui Sun, Guoqiang Yu
  • Patent number: 10770432
    Abstract: A die structure includes a first die having a first surface and a second surface opposite the first surface. The first die includes sidewalls extending between the first and second surfaces. The die structure includes conductive ink printed traces including a first group of the conductive ink printed traces on the first surface of the first semiconductor die. A second group of the conductive ink printed traces are on the second surface of the semiconductor die, and a third group of the conductive ink printed traces are on the sidewalls of the semiconductor die.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10763316
    Abstract: An organic light emitting diode display device includes a substrate including a red pixel region, a green pixel region, and a blue pixel region; a driving thin film transistor and a light emitting diode which are in each of the red pixel region, the green pixel region, and the blue pixel region; and a cholesteric liquid crystal (CLC) layer having an infrared radiation (IR) wavelength in a transmission direction of light emitted from the light emitting diode, wherein the IR wavelength is in a range of 800 nm to 1,100 nm, and the CLC layer has a reflection wavelength of 400 nm to 700 nm at a viewing angle of 40° to 60°.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 1, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Ji-Su Han, Hye-Jeong Park
  • Patent number: 10756255
    Abstract: A device is provided that includes a semiconductor substrate on which a free magnetic element is positioned, which has first and second magnetic domains separated by a domain wall. A first magnet is positioned on the substrate near a first end of the free magnetic element, and has a first polarity and a first value of coercivity. A second magnet is positioned on the substrate near a second end of the free magnetic element, and has a second polarity, antiparallel relative to the first polarity, and a second value of coercivity different from the first value of coercivity.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mingyuan Song, Chwen Yu, Shy-Jay Lin
  • Patent number: 10756020
    Abstract: A fabric-based item may include fabric layers and other layers of material. An array of electrical components may be mounted in the fabric-based item. The electrical components may be mounted to a support structure such as a flexible printed circuit. The flexible printed circuit may have a mesh shape formed from an array of openings. Serpentine flexible printed circuit segments may extend between the openings. The electrical components may be light-emitting diodes or other electrical devices. Polymer with light-scattering particles or other materials may cover the electrical components. The flexible printed circuit may be laminated between fabric layers or other layers of material in the fabric-based item.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 25, 2020
    Assignee: Apple Inc.
    Inventors: Daniel D. Sunshine, Paul S. Drzaic, Daniel A. Podhajny, David M. Kindlon, Hoon Sik Kim, Kathryn P. Crews, Yung-Yu Hsu
  • Patent number: 10741642
    Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
  • Patent number: 10727319
    Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Wen-Cheng Lo, Sun-Jay Chang
  • Patent number: 10720086
    Abstract: A display device including a plurality of vertical type semiconductor light-emitting diodes; a plurality of horizontal type semiconductor light-emitting diodes; a first wiring formed on a substrate and including a plurality of electrode lines, a first electrode line being connected with first conductive electrodes of the vertical type semiconductor light-emitting diodes and a second electrode line being connected with first conductive electrodes of the horizontal type semiconductor light-emitting diodes; a second wiring spaced apart from and crossing the first wiring and electrically connected with second conductive electrodes of the vertical type semiconductor light-emitting diodes; and a third wiring formed on the substrate, electrically connected with the second wiring, and connected with second conductive electrodes of the horizontal type semiconductor light-emitting diodes.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 21, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Hwanjoon Choi, Yonghan Lee
  • Patent number: 10714633
    Abstract: In a transistor including an oxide semiconductor film, field-effect mobility and reliability are improved. A semiconductor device includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same elements. The second oxide semiconductor film includes a region having a higher carrier density than the first oxide semiconductor film and the third oxide semiconductor film.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10714332
    Abstract: A method for forming a silicon nitride film to cover a stepped portion formed by exposed surfaces of first and second base films in a substrate, includes: forming a nitride film or a seed layer to cover the stepped portion, wherein the nitride film is formed by supplying, to the substrate, a nitrogen-containing base-film nitriding gas for nitriding the base films, exposing the substrate to plasma and nitriding the surface of the stepped portion, and the seed layer is composed of a silicon-containing film formed by supplying a raw material gas of silicon to the substrate and is configured such that the silicon nitride film uniformly grows on the surfaces of the base films; and forming the silicon nitride film on the seed layer by supplying, to the substrate, a second raw material gas of silicon and a silicon-nitriding gas for nitriding silicon.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: July 14, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Noriaki Fukiage, Takayuki Karakawa, Toyohiro Kamada, Akihiro Kuribayashi, Takeshi Oyama, Jun Ogawa, Kentaro Oshimo, Shimon Otsuki, Hideomi Hane
  • Patent number: 10707216
    Abstract: Provided is a method for manufacturing a semiconductor device including: patterning a substrate to form a plurality of active patterns including two adjacent active patterns having a first trench therebetween; forming a semiconductor layer on the plurality of active patterns to cover the plurality of active patterns; forming a device isolation layer on the semiconductor layer to cover the semiconductor layer for oxidization and fill the first trench; patterning the device isolation layer and the plurality of active patterns so that a second trench intersecting the first trench is formed and the two active patterns protrudes from the device isolation layer in the second trench; and forming a gate electrode in the second trench. Here, a first thickness of the semiconductor layer covering a top surface of each of the two active patterns is greater than a second thickness of the semiconductor layer covering a bottom of the first trench.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmi Yoon, Chunhyung Chung
  • Patent number: 10707450
    Abstract: Disclosed is an OLED thin film packaging structure, including: a TFT substrate, an OLED, a first barrier layer, a first buffer layer, and a second barrier layer. The OLED is disposed on the TFT substrate. The first barrier layer is disposed on four sides and an upper surface of the OLED. The first buffer layer is disposed on an upper surface of the first barrier layer, and the second barrier layer covers the first barrier layer and the first buffer layer. An OLED thin film packaging method includes steps of: preparing a first barrier layer and a first buffer layer by using a first mask, and preparing a second barrier layer by using a second mask, thereby reducing a quantity of times for changing a mask, reducing a quantity of particles, and improving a thin film packaging effect.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 7, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Wei Yu
  • Patent number: 10707379
    Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary, which has a shape including a plurality of interconnected fingers. The n-type semiconductor layer can have a shape at least partially defined by the mesa boundary. A first n-type contact layer can be located adjacent to another portion of the n-type semiconductor contact layer, where the first n-type contact layer forms an ohmic contact with the n-type semiconductor layer. A second contact layer can be located over a second portion of the n-type semiconductor contact layer, where the second contact layer is formed of a reflective material.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 7, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Maxim S. Shatalov, Mikhail Gaevski, Michael Shur