Abstract: A die includes fins extending in a first direction, a gate formed over the fins, the gate extending in a second direction that is perpendicular to the first direction, a first source/drain contact layer formed over the fins and extending in the second direction, and a second source/drain contact layer formed over the fins and extending in the second direction, wherein the first source/drain contact layer and the second source/drain contact layer are on opposite sides of the gate. The die also includes a first source/drain metal layer electrically coupled to the first source/drain contact layer, and a second source/drain metal layer electrically coupled to the second source/drain contact layer, wherein the first source/drain metal layer and the second source/drain metal layer do not overlap one or more of the fins.

Abstract: There is provided a semiconductor device and a method of manufacturing the same.

Abstract: A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.

Abstract: The present disclosure provides example embodiments relating to conductive features, and methods of forming the conductive features, that have differing dimensions. In an embodiment, a structure includes a substrate, a dielectric layer over the substrate, and first and second conductive features through the dielectric layer to first and second source/drain regions, respectively, on the substrate. The first conductive feature has a first length along a longitudinal axis of the first conductive feature and a first width perpendicular to the first length. The second conductive feature has a second length along a longitudinal axis of the second conductive feature and a second width perpendicular to the second length. The longitudinal axis of the first conductive feature is aligned with the longitudinal axis of the second conductive feature. The first width is greater than the second width, and the first length is less than the second length.

Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

Abstract: A display apparatus with low power consumption and high image quality is provided. The display apparatus includes a light-emitting element, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. Preferably, one electrode of the light-emitting element is electrically connected to one of a source and a drain of the first transistor; the one electrode of the light-emitting element is electrically connected to one electrode of the first capacitor; a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor; the gate of the first transistor is electrically connected to one electrode of the second capacitor; the other electrode of the second capacitor is electrically connected to the other electrode of the first capacitor; and the other electrode of the second capacitor is electrically connected to one of a source and a drain of the third transistor.

Abstract: The present disclosure provides an image sensor, a manufacturing method thereof and a display device. The image sensor includes: a substrate; a first photodiode and a second photodiode located on the substrate, the first photodiode including a first electrode, a second electrode, and a first semiconductor structure located between the first electrode and the second electrode, the second photodiode including a third electrode, a fourth electrode, and a second semiconductor structure located between the third electrode and the fourth electrode, the first electrode being connected to the third electrode, the second electrode being connected to the fourth electrode; a switching thin film transistor, a source or a drain of the switching thin film transistor being connected to the second electrode or the first electrode; a capacitor connected in parallel with the first photodiode and the second photodiode for storing electrical signals when the image sensor receives light.

Abstract: Display device has display region of pixels including first pixel arranged in central portion of the display region and second pixel arranged between the first pixel and the edge of the display region. Each pixel includes first and second light emitting elements. Color filter layer is arranged on the first and second light emitting elements. The first light emitting element includes first color filter, and opening of the first light emitting element is defined by the color filter layer. The second light emitting element includes second color filter and having spectral transmittance characteristic different from the first color filter. Ratio of size of the opening to size of light emitting region of the first light emitting element is smaller in the second pixel than in the first pixel.

Abstract: A metal-oxide-semiconductor (MOS) capacitor can include a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, a conductive layer formed over at least a portion of the oxide layer, a first terminal connected with the surface of the substrate, and a second terminal connected with the conductive layer. The oxide layer can be connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal. Each of the first terminal and the second terminal can be exposed along the surface of the substrate for surface mounting the capacitor. The MOS capacitor can exhibit excellent high frequency performance. For example, an insertion loss of the MOS capacitor can be greater than about ?0.75 dB for frequencies ranging from about 5 GHz to about 40 GHz.

Abstract: In order to improve energization capacity, minority carrier injection efficiency is increased. In a semiconductor device, an IGBT includes a first drift layer, a collector region, a base region, an emitter region, an insulating film, a gate electrode, and a first high carrier lifetime region formed at a position closer to the collector region than the base region and having a longer carrier lifetime than the first drift layer. An FWD includes a second drift layer, an anode region, and a second high carrier lifetime region formed at a position closer to the anode region than a lower surface of the second drift layer and having a longer carrier lifetime than the second drift layer.

Abstract: A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al2O3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al2O3—HfO2. Additional examples are from the group consisting of ZrO2, HfZrO2, silicon or other doped HfO2 or ZrO2, ZrTiO2, HfTiO2, La2O3, Y2O3, Ga2O3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO2, silicon or other doped HfO2 or ZrO2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

Abstract: A thin film transistor and a manufacturing method thereof are provided. The thin film transistor includes a composite electrode including a barrier layer and an electrode layer. The barrier layer has a protruding part relative to the electrode layer, an orthographic projection of the protruding part on the composite electrode protrudes beyond an orthographic projection of the electrode layer on the composite electrode, and a length of the protruding part ranges from 0.3 um to 0.5 um. The thin film transistor and the manufacturing method thereof of the present disclosure can relieve light leakage, thereby improving a contrast ratio of products.

Abstract: A laminated structure which at least includes one laminated unit, the lamination unit includes: a first metal oxide layer and a second metal oxide layer which are oppositely arranged, and a third metal layer arranged between the first metal oxide layer and the second metal oxide layer, and a third metal oxide film is respectively formed between the first metal oxide layer and the third metal layer, and between the second metal oxide layer and the third metal layer.

Abstract: A nano-vacuum tube (NVT) transistor comprising a source having a knife edge, a drain, and a channel formed between the source and the drain, the channel having a width to provide a pseudo-vacuum in a normal atmosphere. The NVT transistor utilizing a space charge plasma formed at the knife edge within the channel.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

Abstract: Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.