Abstract: A method for aligning a semiconductor wafer is provided. The method includes providing the semiconductor wafer having two alignment marks formed on an active region or on an edge region of the semiconductor wafer. An included angle that is formed between the two alignment marks in a circumferential direction of the semiconductor wafer is between about 12 degrees and about 36 degrees. The method further includes receiving the detection signal reflected from at least one of the first alignment mark and the second alignment mark. The method also includes determining a parameter by a control system based on the received detection signal and moving the semiconductor wafer according to the parameter.

Abstract: A semiconductor package includes a substrate, a die, an insulating die attach film, a dummy die, a conductive layer, and an electrically conductive molding compound or encapsulant. The first surface of the substrate includes a plurality of internal leads, and the second surface of the substrate includes a plurality of external electrically conductive pads and an electrically conductive ground terminal. A non-conductive flow over wire die attach film is placed to surround and encase the die. The dummy die overlies the die and a conductive layer overlies the dummy die. The electrically conductive molding compound is formed to encase the various components of the semiconductor device. The electrically conductive molding compound is electrically coupled to the electrically conductive ground terminal and the conductive layer forming an EMI shield for the die in the package.

Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.

Abstract: The present invention provides a prefabricated substrate of array substrate, a vapor deposition method, an array substrate and a display apparatus, which can solve a problem that there is a waste of material in a vapor deposition process of the prior art. The prefabricated substrate comprises a plurality of sub-pixel units, each sub-pixel unit comprising a drive unit and a sub-pixel electrode connected with the drive unit, wherein, the drive unit is also connected with a data line and a gate line, and is used for transferring a data voltage signal outputted from the data line to the sub-pixel electrode when the gate line is strobed. The sub-pixel unit further comprises a switch unit connected with the data line and the sub-pixel electrode The switch unit is used for adjusting voltage of the sub-pixel electrode under control of a switch signal outputted from a switch signal line.

Abstract: Disclosed herein is a light emitting device manufactured by separating a growth substrate in a wafer level. The light emitting device includes: a base; a light emitting structure disposed on the base; and a plurality of second contact electrodes disposed between the base and the light emitting structure, wherein the base includes at least two bulk electrodes electrically connected to the light emitting structure and an insulation support disposed between the bulk electrodes and enclosing the bulk electrodes, the insulation support and the bulk electrodes each including concave parts and convex parts engaged with each other on surfaces facing each other, and the convex parts including a section in which a width thereof is changed in a protrusion direction.

Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Abstract: A semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or grown epitaxial silicon for controlled drift region thickness and fast switching speed.

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

Abstract: An electronic component integrated substrate includes a first substrate including a first pad, a first solder resist layer provided with a first open portion that selectively exposes the first pad, and a connection pad formed on the first solder resist layer, and electrically connected to the first pad; a second substrate, stacked on the first substrate, including a second pad, and a second solder resist layer formed on the second pad and provided with a second open portion that selectively exposes the second pad; an electronic component mounted on the first substrate and sandwiched between the first substrate and the second substrate; and a substrate connection member that electrically connects the connection pad and the second pad with each other, the diameter of the connection pad being larger than each of the diameter of the first pad and the diameter of the second open portion.

Abstract: A flow measuring device, comprising a container for receiving a flow of liquid, a plurality of optical sensors associated with the container, each of the plurality of optical sensors producing an output signal dependent upon the presence of liquid reaching a level in the container associated with each optical sensor, means for modifying the output signal in accordance with at least one predetermined temperature compensation factor, and means for calculating a flow rate from the time at which the liquid traverses between two levels in the container.

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

Abstract: A patterns forming method begins with performing a lithography process on a photoresist film with a photomask having first apertures in a first mask region and second apertures in a second mask region to respectively form first main features and dummy features, on which the second mask region is located between the border of the photomask and the first mask region, and a size of each of the first apertures is greater than a size of each of the second apertures. Subsequently, a material is filled into the first main features to respectively form second main features and into the dummy features to seal the dummy features. Then, a substrate is etched to form patterned features by using the photoresist film having the second main features.

Abstract: A sensor unit including a first semiconductor component and a second semiconductor component, the first semiconductor component including a first substrate and a sensor structure. The second semiconductor component includes a second substrate, the first and second semiconductor components being connected to each other with the aid of a wafer connection, the sensor unit having a decoupling structure, which is configured in such a way that the sensor structure is decoupled thermally and/or mechanically from the second semiconductor component.

Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

Abstract: A metallization scheme for vertical field effect transistors (FETs) is provided. By forming lower-level local interconnects connecting source regions located at bottom portions of semiconductor fins, and upper-level interconnects connecting adjacent metal gates located along sidewalls of channel regions of the semiconductor fins, electrical connections to the source regions and the metal gates can be provided through the lower-level local interconnects and the upper-level local interconnects, respectively. As a result, gate, source and drain contact structures are formed on the same side of vertical FETs.

Abstract: Disclosed is a method for forming a semiconductor device and a semiconductor device. The method includes: in a SiC semiconductor body, forming crystal defects in a first semiconductor region by introducing non-doping particles into the semiconductor body; and forming a second semiconductor region such that there is a pn junction between the first semiconductor region and the second semiconductor region.