Abstract: An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN3 in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside down NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e.

Abstract: The present invention improves the characteristic of a trench-type vertical MOSFET. When a trench 23 serving as a gate 25 is formed, it is made in a shape of ".gamma." which is convex toward the inside of the trench. Thus, the surface area of the trench is reduced so that both gate-source capacitance and gate-drain capacitance can be reduced, thereby shortening the switching time of the MOSFET.

Abstract: A GaN/AlGaN heterojunction bipolar phototransistor having AlGaN contact, i-GaN absorbing, p-GaN base and n-GaN emitter layers formed, in that order, on a UV transparent substrate. The phototransistor has a gain greater than 10.sup.5. From 360 nm to 400 nm, eight orders of magnitude drop in responsivity was achieved. The phototransistor features a rapid electrical quenching of persistent photoconductivity, and exhibits high dark impedance and no DC drift. By changing the frequency of the quenching cycles, the detection speed of the phototransistor can be adjusted to accommodate specific applications. These results represent an internal gain UV detector with significantly improved performance over GaN based photo conductors.

Abstract: In the semiconductor substrate, an insulation film designed for the element separation is formed. A gate insulation film and a floating gate electrode are formed in the element region surrounded by the insulation film for the element separation. The lower portions of the four lateral surfaces of the floating gate electrode are covered by the interlayer insulation film. The interlayer insulation film is made thicker than the gate insulation film. The upper surface of the floating gate electrode and the upper portions of the four lateral surfaces are covered by the control gate electrode. The upper surface of the control gate electrode is made flat. With this structure, the electrostatic capacitance between the floating gate electrode and the control gate electrode can be increased and stabilized.

Abstract: A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer's performance and/or yield requirements.

Abstract: By using wafer fusion, various structures for photodetectors and photodetectors integrated with other electronics can be achieved. The use of silicon as a multiplication region and III-V compounds as an absorption region create photodetectors that are highly efficient and tailored to specific applications. Devices responsive to different regions of the optical spectrum, or that have higher efficiencies are created.

Abstract: A ballasted transistor structure reduces thermal runaway. A heterojunction bipolar junction transistor array includes a plurality of transistors, each having an emitter, a base and a collector. Each of the bases is an alloy of silicon and germanium and each of the collectors and emitters is silicon. A ballast resistor, of doped silicon, that prevents thermal runaway, is electrically connected to each of the collectors.

Abstract: A semiconductor laser device comprises a GaAs substrate, a first cladding layer having either one of p-type electrical conductivity and n-type electrical conductivity, a first optical waveguide layer, an In.sub.x2 Ga.sub.1-x2 As.sub.1-y2 P.sub.y2 first barrier layer, an In.sub.x3 Ga.sub.1-x3 As.sub.1-y3 P.sub.y3 quantum well active layer, an In.sub.x2 Ga.sub.1-x2 As.sub.1-y2 P.sub.y2 second barrier layer, a second optical waveguide layer, and a second cladding layer having the other electrical conductivity, the layers being overlaid in this order on the substrate. Each cladding layer and each optical waveguide layer have compositions, which are lattice matched with the substrate. Each of the first and second barrier layers has a tensile strain with respect to the substrate and is set such that a total layer thickness of the barrier layers may be 10 nm to 30 nm, and a product of a strain quantity of the tensile strain and the total layer thickness may be 0.05 nm to 0.2 nm.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a plurality of first transistors formed over the semiconductor substrate in a matrix configuration, each of the first transistors having a channel region; a plurality of second transistors formed over the semiconductor substrate in a matrix configuration, each of the second transistors having a channel region; and a plurality of word lines formed in parallel in a first direction, each of the word lines functioning as a word line and a gate electrode. At least two channel regions of the plurality of first transistors make contact in the first direction; and at least two channel regions of the plurality of second transistors make contact in a second direction.

Abstract: The invention is to develop a high-speed low power consumption resonant tunneling element--a superlatticed negative-differential-resistance (NDR) functional transistor. The proposed element exhibits amplification and obvious NDR phenomena simultaneously. In this element, the emitter region includes 5-period GaInAs/AlInAs super lattice resonant tunneling and emitter layers. Since the emitter--base interface is of homojunction, the collector--emitter offset voltage (V.sub.CE, offset) may be lowered down significantly. In addition, the produced infinitesimal potential (.DELTA.Ev) at GaInAs/AlInAs interface due to heterojunction in discrete valence bands may be applied as barriers to prohibit holes flow from base towards emitter. By doing so, the base current is remarkably depressed so as to elevate efficiency of emitter injection as well as current gain.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signal unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die.

Abstract: In forming an electrode on a silicon oxide film on a semiconductor substrate through a silicon oxide film, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers. The portion of the gate electrode is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and of crystallizing (recrystallizing) this amorphous material. Depositing of the amorphous layers is carried out a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and crystallizing the amorphous material are repeated, whereby a laminated structure of polycrystalline layers having a necessary film thickness is obtained.

Abstract: A CMOS sensor structure and method of manufacture that includes the fabrication of a special shallow trench isolation structure. Besides isolating the active region for forming the CMOS sensor device, the shallow trench isolation structure has a special reflective plug embedded inside capable of reflecting incoming light onto the sensitive region of the CMOS sensor. Hence, the interactive length of incoming light with the light sensitive region can be increased, thereby increasing the contrast ratio and light sensitivity of the CMOS sensor.

Abstract: Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used to make electrical contact to ground. Electrical circuit elements in the top surface of the integrated circuit are selectively grounded or isolated by the choice of connection to a via or pedestal, respectively.

Abstract: A metal-semiconductor-metal photodetector including an absorbent layer, a barrier layer of greater forbidden band energy on which there are deposited Schottky electrodes and a transition layer of graded composition, the photodetector including a doping plane situated in the vicinity of the join between the absorbent layer and the transition layer of graded composition.

Abstract: A cold end and a hot end are demarcated in a first thermoelectric semiconductor member. A first member made from metal or a semiconductor is connected to the cold end of the first thermoelectric semiconductor member. The first member is made from a material wherein, heat absorption occurs when first carriers comprising either electrons or holes are injected from the first member into the first thermoelectric semiconductor member. The first carriers transported to the hot end of the first thermoelectric semiconductor member are gathered into a light-emitting region. The light-emitting region is made from a semiconductor material. In this light-emitting region, light emission due to recombination between electrons and holes occurs.

Abstract: A semiconductor light emitting device has a light emitting layer forming portion formed on the substrate and having an n-type layer and a p-type layer to provide a light emitting layer. A window layer is formed on a surface side of the light emitting layer forming portion. The window layer is formed of AlyGal-yAs (0.6.ltoreq.y.ltoreq.0.8) auto-doped in a carrier concentration of 5.times.10.sup.18 -3.times.10.sup.19 cm.sup.-3. The resulting semiconductor light emitting device is free of degradation in crystallinity due to p-type impurity doping, thereby provide a high light emitting efficiency and brightness without encountering device degradation or damage.

Abstract: An intrinsic device section is provided by laminating a drain area, an intermediate area, and a source area above a GaAs substrate and by forming a channel area at one oblique surface thereof. A drain electrode ohmic connected to the drain area extends toward the output side, a source electrode ohmic connected to the source area extends above the drain electrode with a dielectric layer placed therebetween, and thereby an output micro-wave transmission line is formed. A gate electrode Schottky connected to the channel area extends toward the input side, the source electrode extends above the drain electrode with the dielectric layer placed therebetween, and thereby an input micro-wave transmission line formed.

Abstract: A light emitting diode includes a double hetero structure containing an upper cladding layer with a graded composition. The light emitting diode comprises a GaAs substrate, a first ohmic contact to the substrate, an AlGaInP lower cladding layer formed on the GaAs substrate, an AlGaInP active layer formed on the lower cladding layer, an AlGaInP upper cladding layer formed on the active layer and a second ohmic contact. The AlGaInP upper cladding layer has a graded composition which increases the LED brightness and decreases the forward bias voltage of the light emitting diode. The graded composition can also be used in the upper semiconducting layer of a conventional p-n junction light emitting diode.

Abstract: There is disclosed an insulated gate bipolar transistor which includes a p type semiconductor region (11) formed in a surface of an n.sup.- semiconductor layer (3) by double diffusion in corresponding relation to a p type base region (4) of an IGBT cell adjacent thereto, and an emitter electrode (9) formed on and connected to the p type semiconductor region (11) through a contact hole (CH.sub.P) having a width (W.sub.ch2) which is greater than a width (W.sub.ch1) of a contact hole (CH.sub.1), thereby preventing device breakdown due to latch-up by the operation of a parasitic thyristor during an ON state and during an ON-state to OFF-state transition even if main and control electrodes in an active region are reduced in size.