Patents Examined by William A. Mintel
  • Active pixel sensor integrated with a pinned photodiode
    Patent number: 6100551
    Abstract: The optimization of two technologies (CMOS and CCD) wherein a pinned photodiode is integrated into the image sensing element of an active pixel sensor. Pinned photodiodes are fabricated with CCD process steps into the active pixel architecture. Charge integrated within the active pixel pinned photodiode is transferred into the charge sensing node by a transfer gate. The floating diffusion is coupled CMOS circuitry that can provide the addressing capabilities of individual pixels. Alternatively, a buried channel photocapacitor can be used in place of the pinned photodiode.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: August 8, 2000
    Assignee: Eastman Kodak Company
    Inventors: Paul P. Lee, Robert M. Guidash, Teh-Hsuang Lee, Eric G. Stevens
  • Quantum WELL MOS transistor and methods for making same
    Patent number: 6091076
    Abstract: A new quantum well MOS transistor is described along with a processes for manufacturing it. In this transistor, the source and drain areas are separated from the channel by sufficiently thin insulating layers to enable the passage of charge carriers by the tunnel effect. Each of the source and drain areas is separated from the substrate by an electrically insulating layer that is sufficiently thick to prevent charge carriers from passing through this insulating layer.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: July 18, 2000
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Simon Deleonibus
  • Electrostatic discharge protection for integrated circuit sensor passivation
    Patent number: 6091082
    Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: July 18, 2000
    Assignee: STMicroelectronics, Inc.
    Inventors: Danielle A. Thomas, Frank Randolph Bryant
  • Semiconductor device with tantalum and ruthenium
    Patent number: 6091099
    Abstract: Disclosed is a semiconductor device, comprising a semiconductor substrate, a cell transistor formed in the semiconductor substrate, an interlayer dielectric film in which is formed a contact hole communicating with a part of the cell transistor, a contact plug buried in the contact hole formed in the interlayer dielectric film, a capacitor lower electrode formed of a ruthenium/tantalum laminate film consisting of a tantalum film and a ruthenium film formed on the tantalum film, the lower electrode being formed on interlayer dielectric film and connected to the contact plug, a capacitor dielectric film formed on the ruthenium film included in the capacitor lower electrode and consisting of a metal oxide, and a capacitor upper electrode formed on the capacitor dielectric film, the ruthenium film exhibiting (00n) dominant orientation, where n denotes a positive integer.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: July 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Kiyotoshi, Kazuhiro Eguchi
  • High density NAND structure nonvolatile memories
    Patent number: 6091100
    Abstract: The present invention includes pad oxides that are separated from each other and on a substrate. First isolations are formed on the pad oxides. Second isolations are formed on the substrate, between the pad oxides. Floating gates are formed on the second isolations and between the first isolations. Third isolations are formed at the top of the floating gates. A word line is formed on the first isolations and on the third isolations. Bit lines are formed in the substrate and under the first isolations.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: July 18, 2000
    Assignee: Texas Instruments - Acer Incorporated
    Inventor: Shye-Lin Wu
  • Evaluation method for wirings of semiconductor device
    Patent number: 6091080
    Abstract: Electromigration (EM) of a multilayer wiring is evaluated accurately and efficiently. A capacitance measuring wiring is disposed through the third insulator film in parallel to the second testing wiring. A stress current is sent to the second testing wiring toward the first testing wiring for a period and subsequently the capacitance of the capacitor composed of the second testing wiring and the capacitance measuring wiring is measured. The volume of voids in the second testing wiring is obtained from the ratio of this capacitance and the capacitance before letting the stress current flow. EM is evaluated by defining the wiring life span by using this volume.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: July 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takamasa Usui
  • Semiconductor device including a crystalline silicon film
    Patent number: 6091115
    Abstract: A semiconductor device having a CMOS structure comprising N-channel type and P-channel type insulated gate semiconductor devices combined in a complementary manner, wherein the threshold voltage of the insulated gate semiconductor devices is controlled by using the difference in work function between the gate electrode and the active layer. The present semiconductor device has excellent uniformity and reproducibility.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: July 18, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film
    Patent number: 6091081
    Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventors: Yoshihisa Matsubara, Ko Noguchi, Shinya Ito, Noriaki Oda, Akira Matsumoto, Takashi Ishigami, Masahiko Nakamae, Tadahiko Horiuchi, Kazuhiko Endo, Toru Tatsumi, Yoshishige Matsumoto
  • Semiconductor light emitting device
    Patent number: 6091084
    Abstract: A semiconductor light emitting device has a light emitting chip and a conductive member. A light emitting chip is formed by an insulating substrate. A semiconductor layered portion has semiconductor layers forming a light emitting layer grown on the insulating substrate. A first electrode (p-side electrode) is formed in electrical connection with a first conductivity type semiconductor layer on a surface side of the semiconductor layered portion. A second electrode (n-side electrode) is formed in electrical connection with a second conductivity type semiconductor layer at a position exposed by partly etching the semiconductor layered portion. The light emitting chip is adhered at a backside of the insulating substrate to the conductive member through a conductive adhesive, and the conductive member is electrically connected to the second electrode.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: July 18, 2000
    Assignee: Rohm Co., Ltd.
    Inventor: Takehiro Fujii
  • Rare-earth schottky diode structure
    Patent number: 6087702
    Abstract: A method for forming a Schottky diode structure is disclosed. The method includes the steps of: a) Providing a substrate; b) forming a rare-earth containing layer over the substrate; and c) forming a metal layer over the rare-earth containing layer. The Schottky diode structure with a rare-earth containing layer has the properties of high-temperature stability, high Schottky barrier height (SBH), and low reverse leakage current.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: July 11, 2000
    Assignee: National Science Council
    Inventors: Liann-Be Chang, Hang-Thung Wang
  • Trench MOSFET having improved breakdown and on-resistance characteristics
    Patent number: 6084264
    Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N drain region is implanted through the bottom of the trench into the P-epitaxial layer, and after a diffusion step extends between the N+ substrate and the bottom of the trench. The junction between the N drain region and the P-epitaxial layer extends between the N+ substrate and a sidewall of the trench. In some embodiments the epitaxial layer can have a stepped doping concentration or a threshold voltage adjust implant can be added. Alternatively, the drain region can be omitted, and the trench can extend all the way through the P-epitaxial layer into the N+ substrate. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: July 4, 2000
    Assignee: Siliconix Incorporated
    Inventor: Mohamed N. Darwish
  • Single crystal silicon sensor with high aspect ratio and curvilinear structures
    Patent number: 6084257
    Abstract: In one aspect, the invention provides semiconductor sensor which includes a first single crystal silicon wafer layer. A single crystal silicon structure is formed in the first wafer layer. The structure includes two oppositely disposed substantially vertical major surfaces and two oppositely disposed generally horizontal minor surfaces. The aspect ratio of major surface to minor surface is at least 5:1. A carrier which includes a recessed region is secured to the first wafer layer such that said structure is suspended opposite the recessed region.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: July 4, 2000
    Assignee: Lucas NovaSensor
    Inventors: Kurt E. Petersen, Nadim Maluf, Wendell McCulley, John Logan, Erno Klaasen, Jan M. Noworolski
  • Heterojunction bipolar transistor with ballast resistor
    Patent number: 6081003
    Abstract: A heterojunction bipolar transistor is provided with a ballast resistor layer in an emitter layer which prevents the current amplification factor .beta. from decreasing. The n-GaAs carrier supply layer having a specified carrier concentration is formed between the ballast resistor layer and the n-AlGaAs layer.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: June 27, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichi Miyakuni, Teruyuki Shimura
  • Semiconductor integrated circuit
    Patent number: 6081005
    Abstract: The present invention is a semiconductor integrated circuit capable of reducing a cross talk noise produced between data buses. A typical semiconductor integrated circuit of the present invention comprises a plurality of data buses which are formed in an insulating film on a semiconductor substrate and arranged substantially in parallel with one another and an extension portion extended from a given data bus of the plurality of data buses wherein the extension portion is spaced away from an adjacent data bus.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: June 27, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Chikashi Fuchigami, Tsutomu Kato, Hidetoshi Ikeda, Yoshio Iihoshi
  • Nitride semiconductor light emitting device
    Patent number: 6081001
    Abstract: A luminous intensity of a semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors is improved by having a thickness d of a light emitting layer (active layer) of the semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors ranging from 0.3 nm to 1.5 nm.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: June 27, 2000
    Assignee: Sony Corporation
    Inventors: Kenji Funato, Tsunenori Asatsuma, Hiroji Kawai
  • Electrostatic discharge protection bus/die edge seal
    Patent number: 6078068
    Abstract: Disclosed is an integrated circuit chip having an improved ESD protection structure. The integrated circuit chip includes a core logic region having a plurality of transistor devices that are interconnected to form a specific integrated circuit device. A plurality of input/output cells are defined along a periphery of the integrated circuit chip. An ESD bus die edge seal that defines a single ring around the periphery of the integrated circuit chip is provided. The ESD bus die edge seal is positioned outside of the plurality of input/output cells closest to a physical outer edge of the integrated circuit chip. Further, a plurality of (Vss) supply cells are contained in selected ones of the plurality of input/output cells. And, a plurality of ESD cross-coupled diodes are connected between the plurality of (Vss) supply cells and the ESD bus die edge seal.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: June 20, 2000
    Assignee: Adaptec, Inc.
    Inventor: Ronald Kazuo Tamura
  • Light emitting diode with patterned electrode
    Patent number: 6078061
    Abstract: The opening portion as the pattern shift detecting portion is formed in the insulating layer so that an edge of the electrode pattern extends to the opening portion when the electrode pattern shifts and the contact resistivity between the light emitting portion and the electrode pattern increases more than the predetermined value during the patterning process. If the electrode pattern shifts to a direction of the scribe line, the electrode pattern is electrically connected to the P-type diffusion region via the pattern shift detecting portion. As a result, the electrode pattern is shorted an N-type electrode pattern via the P-type diffusion region and the N-type GaAsP/GaAs substrate Therefore, the light emitting diode can precisely detect inferior products without visual inspection.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: June 20, 2000
    Assignee: Oki Data Corporation
    Inventor: Keiichi Koya
  • Semiconductor device having mutually different two gate threshold voltages
    Patent number: 6078067
    Abstract: On a semiconductor substrate, a channel layer, an electron supply layer, a third semiconductor layer, a second etching stopper layer, a second semiconductor layer and a first etching stopper layer and a first semiconductor layer are grown in sequential order to form E-type and D-type FETs. The third semiconductor layer and the second semiconductor layer have equal layer thickness, and the second etching stopper layer and the first etching stopper layer have the equal layer thickness. Thus, Vth of the E-type and D-type FETs can be controlled at the predetermined value with high reproduction ability.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: June 20, 2000
    Assignee: NEC Corporation
    Inventor: Hirokazu Oikawa
  • Precision breaking of semiconductor wafer into chips by applying an etch process
    Patent number: 6075280
    Abstract: This invention discloses a novel method for separating a semiconductor wafer into a plurality of integrated circuit (IC) chips. The separation is carried out along scribe lines between the IC chips. The method includes steps of (a) forming a photoresist layer on the semiconductor wafer; (b) performing a photolithography process for removing the photoresist layer above the scribe lines between the IC chips; (c) performing an etch process for removing a dielectric layer above the scribe lines between the IC chips for exposing the scribe lines on the semiconductor wafer; (d) performing a wet chemical etch process to anisotropically etch the semiconductor wafer into a V-shaped groove in the scribe lines; and (e) applying a mechanical force to break the semi-conductor wafer along the V-shaped grooves in the scribe lines thus separating the semiconductor wafer into a plurality of IC chips.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: June 13, 2000
    Assignee: Winbond Electronics Corporation
    Inventors: Hao-Chieh Yung, Gene Jing-Chiang Chang
  • Monolithic x-ray image detector and method of manufacturing
    Patent number: 6072224
    Abstract: An x-ray imaging detector comprised of read-out electronics and PIN diodes formed on a high resistivity silicon-on-insulator substrate that permits cell pitches as small as 20 microns. The read-out electronics are fabricated in the thin, top silicon layer of the SOI substrate. The read-out electronics produced provide circuits such as integrators and transimpedance amplifiers which are required to transform the electrical current from PIN diode detectors into an analog voltage. The anodes of the PIN sensor diodes are formed by etching through an oxide barrier layer in the substrate and implanting a heavily doped p+ region into a high resistivity intrinsic silicon layer. X-ray imaging detectors produced by the methods disclosed herein can be assembled into multi-chip modules that can be used in a large panel x-ray imaging apparatus.
    Type: Grant
    Filed: December 27, 1997
    Date of Patent: June 6, 2000
    Assignee: Mission Research Corporation
    Inventors: Scott M. Tyson, Eugene L. Atlas