Abstract: A method and structure for adjustment of the threshold voltage of a vertical metal-oxide-semiconductor transistor. Chemical vapor deposition of doped silicon dioxide and annealing are used to form a voltage-threshold-adjustment region in at least the channel layer of the transistor adjacent to the trench wall.

Abstract: Island layers defined by grooves are formed on a p.sup.+ -type silicon substrate. One memory cell having a MOS capacitor and a MOSFET transistor is formed in each island layer. The MOS capacitor is buried in a groove surrounding the island layer and has a capacitor electrode insulatively provided over the bottom surface of the groove and an n.sup.- -type semiconductor layer formed in a ring-shaped manner in the side surface region of the groove and facing the capacitor electrode. The MOSFET has a ring-shaped gate electrode for in the groove to be insulatively stacked over the capacitor electrode. The gate electrode faces a p-type channel region formed in a ring-shaped manner in the side surface region of the island layer. Only a drain layer is formed in the top surface region of the island layer.

Abstract: In an integrable Hall element, which includes a semiconductor layer of a single conductive type, a plurality of current electrodes adapted for being connected to an energy source, and wherein at least one current electrode and two sensor electrodes are located on a surface of the Hall element, and the one current electrode has a first connecting contact forming a first energy source pole, the improvement consists in the one current electrode being approximately located in the center of a line connecting the sensor electrodes.

Abstract: A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.

Abstract: A bipolar integrated circuit having a polysilicon contact (26) to a heavily doped graft base region 24g which is spaced from oxide isolation walls 22 by a distance sufficiently small that in operation, the surface portion 37 of the collector region 23 is fully depleted from the graft base region 24g to the oxide isolation 22, so that base-collector capacitance is reduced due to the graft base being smaller than the oxide isolated island and by the absence of capacitance between the sides of the graft base region and the collector, while capacitance between the polysilicon contact 26 and the collector is also decreased by the depleted surface portion 37 of the collector.

Abstract: A three terminal differentially sensitive magnetic diode structure is described. It offers high magnetic sensitivity and utilizes the Lorentz field potential modulation of injected carriers at the emitter. Two base contacts separated from the emitter are employed to derive a signal from the modulation of emitter injection in the presence of a magnetic field.

Abstract: A low alpha-particle-emitting ceramic composite cover which when used in a ceramic integrated circuit package to encapsulate an integrated circuit device, reduces soft errors caused by alpha-particles emitted from the ceramic material. An alpha-particle-absorbing barrier layer is attached to the major portion of the interior surface of the ceramic cover to absorb alpha-particles emitted by the ceramic material. The barrier layer may be an organic polymeric material or an inorganic high purity material. Preferably the barrier layer is a polyimide film which is attached to the ceramic cover by a glass sealant material. Various constructions of the composite cover and ceramic integrated circuit packages utilizing the composite cover are disclosed.

Abstract: A bi-polar transistor structure in a superhigh speed logic integrated circuit, and a process for producing the same are disclosed. The transistor has a substantially coaxial symmetric structure. Single crystal active layers as base and collector regions have peripheries surrounded wholly or partially by respective polycrystalline electrode layers. The polysilicon electrodes have lateral portions and downward depending portions that connect to single crystal layers. The polycrystalline electrode layers are separated from each other by insulation. One process for producing the structure uses only thin film forming techniques and etching techniques to dispose the active layers, an emitter electrode layer, parts of the other electrode layers and parts of the insulating layers inside a recess formed in an insulating layer formed on a substrate. Another process uses a photoetching technique by which polycrystalline layers for base and collector electrodes are patterned.

Abstract: Resonant tunneling semiconductor devices are disclosed useful for transport functions such as switching or amplification, and also for electro-optical conversions. In the structure of these devices, a central potential well is formed of an opposite conductivity type of semiconductor material to two semiconductor layers outside resonant tunneling barriers on each side of the central potential well, such that electrons in the well can tunnel to and from the outside semiconductor layers. The central potential well serves as the base of a three terminal device in transport applications, and as the light responsive portion for electro-optical applications. In one disclosed embodiment, the device is constructed in five layers of the most commonly used gallium-aliminum-arsenide compounds, an n GaAlAs, undoped GaAlAs, p GaAlAs, undoped GaAlAs, and n GaAlAs.

Abstract: A novel process is provided to fabricate interconnections (46c) in transistors (14) having self-aligned, planarized contacts (46s, 40g, 46d) in a novel, completely self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower.A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and p.sup.+ polysilicon plugs.

Abstract: A homojunction bipolar transistor having a superlattice base region comprising alternate layers of extrinsic and intrinsic layers, with extrinsic layers being of the opposite conductivity of the emitter and collector layers of the transistor. The alternate extrinsic and intrinsic layers have substantially different doping levels providing abrupt transitions in the valence and conduction bands between layers. The abrupt transitions result in the energy band gap in the base region being effectively reduced with respect to the band gap in the emitter region. In one embodiment, the effective narrow band gap base transistor is implemented by converting a portion of the upper layers of the superlattice to a homogeneous region by heavily doping the portion to form the emitter of the transistor.

Abstract: A metal-semiconductor field effect transistor device has an active layer formed on a first main surface of a semiconductor substrate with a first gate electrode provided on the active layer in Schottky contact therewith and source and drain electrodes provided on opposite sides of the first gate electrode and in ohmic contact with the active layer so as to define corresponding source and drain regions in the active layer with an active region of the active layer extending therebetween. A second gate electrode including first and second portions is provided in Schottky contact on the active layer, respectively on the exposed surface portion segments thereof intermediate the opposite sides of the first gate electrode and the respective drain and source electrodes associated with the first gate electrode.

Abstract: The integrated structure is formed of various circuital components accomplished by diffusion of dopants in a semiconductor substrate. Each component is located inside a respective insulation recess electrically floating in relation to the substrate and the other components.

Abstract: A new kind of electronic logic circuit, wherein potential wells (e.g. islands of GaAs in an AlGaAs lattice) are made small enough that the energy levels of carriers within the wells are discretely quantized. This means that, when the bias between the wells is adjusted to align energy levels of the two wells, tunneling will occur very rapidly, whereas when the energy levels are not aligned, tunneling will be greatly reduced. In particular, the wells are optimized to have sharp enough resonant tunneling peaks that the change in potential caused by the difference between the number of carriers stored between two adjacent tunnel wells is itself enough to permit or preclude resonant tunneling. Thus, a tremendous variety of logic functions, including all primitive Boolean functions can be embodied in this logic.

Abstract: An integrated logic circuit with complementary transistors which is constructed from cells which form reproductions of logic equations, in which each cell has at least three transistors arranged one next to the other in a row and three complementary transistors arranged one next to the other. Series arrangements of transistors or transistor circuits in one row corrugated to parallel arrangements of transistors or transistor circuits in the other row. This arrangement results in compact layouts which are easy to design with computer assistance. The arrangement is particularly useful for MSI and LSI circuits.

Abstract: The manufacture of monolithic HgCdTe detectors and Si circuitry in an IR focal plane array is achieved by forming a protective layer of SiO.sub.2 or SiN.sub.x on a silicon wafer containing silicon circuits, etching steep-wall recesses into the wafer, selectively depositing epitaxial single-crystal layers of GaAs, CdTe, and HgCdTe in the recesses fabricating HgCdTe IR arrays, and depositing appropriate insulating and conductive interconnection patterns to interconnect the Si devices with one another and the HgCdTe devices with the Si devices. Little or no GaAs, CdTe, and HgCdTe grows on the SiO.sub.2 or SiN.sub.x outside the recesses. Since material grown outside the recess is polycrystalline, it is easily chemomechanically removed.

Abstract: A dielectrically isolated semiconductor device which is substantially planar can be manufactured. The structure is useable for integrated circuits wherein a significant savings in surface area can be obtained over prior techniques. The structure is particularly useful for bipolar integrated circuits wherein a semiconductor substrate with an epitaxial layer thereon contains a buried region partially in the substrate and in the epitaxial layer. The emitter and base regions are located in the epitaxial layer above the buried region. The dielectrically isolating region surrounds the emitter and base region at the surface and extends to a depth wherein it intersects with the buried region to fully isolate the device. The buried region is connected as the collector element of the transistor.

Abstract: A self-aligned, lateral bipolar transistor is disclosed having at least one insulated metal gate for control of the base. The device has a Semiconductor-On-Insulator structure that reduces parasitic capacitances. Proper gate control provides a high and controllable gain of the device and also turns off the parasitic transistors. The device achieves variable, high gains as well as high frequencies due to the use of the gate. It requires no masking or doping manufacturing steps in addition to those used in making standard CMOS circuits, and is CMOS compatible. In a preferred embodiment, a second insulated metal back gate is used to further enhance the operation of the device.

Abstract: A V-MOS FET has a semiconductor body of one conductivity type, a plurality of base regions of the other conductivity type formed in a surface portion of the semiconductor body in a form of matrix having rows and columns, a plurality of source regions of the one conductivity type formed in the base regions, a plurality of auxiliary regions of the other conductivity type formed in the surface portion of said semiconductor body at crossing points of the rows and columns of the base region matrix, a mesh-shape gate electrode formed on region between the source regions to cover the auxiliary regions, a source electrode contacting at least the source regions and a drain electrode contacting a back surface of the semiconductor body.

Abstract: An integrated circuit resistor adjustment network with resistors (R1, R.sub.2, R.sub.3, R.sub.4) which may be paralleled by trimming resistors (R5, R7, R6, R8, respectively) upon electrical "zapping" of Zener diodes (Z1, Z2, Z3, Z4, respectively) connected in series with the trimming resistors. The Zener diodes (Z1, Z4 or Z2, Z3) are connected in inverse series via inverse paralleled diodes (D1, D2 or D3, D4 respectively) which are non-conductive during normal operation, but conduct during higher voltage zapping operation to permit the currents for zapping the Zener diodes to bypass the resistors.