Abstract: A semiconductor device has an emitter potential barrier, a collector potential barrier, a base between the emitter potential barrier and the collector potential barrier, an emitter in contact, through the emitter potential barrier, with the base, and a collector in contact, through the collector potential barrier, with the base. The base has a thin base width capable of generating discrete energy levels of monority carriers therein. Carriers which are minority carriers in the base can be transferred from the emitter via the discrete energy levels in the base to the collector by resonant tunneling at an ultra-high speed.

Abstract: A semiconductor component which comprises a planar structure which has a channel stopper 7 formed at one edge and a field electrode which covers a pn-junction 3 of the planar zones adjoining the edge 4. The blocking voltage can be increased by providing a channel stopper field plate 19 arranged over the channel stopper and an anode field plate 18 arranged over the field electrode and these field plates are spaced a greater distance from the surface 8 of the semiconductor body between the electrodes 18 and 19 and they have over the channel stopper electrode and the gate electrode.

Abstract: In a variable-capacitance diode device consisting of a PN junction, and a semiconductor layer of a first conductivity type, the impurity concentration of which decreases as the depth from the PN junction increases, the semiconductor layer of the first conductivity type is arranged to include, except in the vicinity of the PN junction, at least one such point that the following relationship holds true:Ai.ltoreq.Ai+1 (i=1, 2, . . . , n)where Ai represents impurity concentration of said semiconductor layer of the first conductivity type at a distance Xi as viewed depth-wise of the PN junction.

Abstract: A semiconductor device comprising three recessed portions formed at a very small pitch on the surface of a semiconductor substrate, remaining regions formed between these recessed portions as impurity diffused regions serving as the source and the drain, respectively, and a conductive region as a gate electrode formed through an insulating film within the central recessed portion, and a method of manufacturing such a semiconductor device are disclosed. With this device, its gate length can be made shorter than that in the prior art and the junction leakage is reduced, resulting in miniaturization and an improvement in the characteristics.

Abstract: In a metal-ceramic housing for a high-power GTO, a space-saving auxiliary cathode connection (5a) capable of carrying current is achieved in that it is constructed by embedding in the insulating ring (4) of the housing and is connected directly to the cathode contact plate (9) via its own connecting elements (11, 13, 15).

Abstract: A lightly-doped drain (LDD) structure has conductive shield overlying the lightly-doped drain and source portions to collect and/or remove hot carriers which can otherwise cause instabilities such as gain degradation and threshold voltage shifts in short-channel MOS devices. The hot carriers eventually deteriorate the performance of the transistor to the point where the transistor provides insufficient performance. Thus, the lifetime of a transistor is affected by the degradation caused by the formation of hot carriers. The lifetime is increased by collecting the hot carriers in the conductive material over the lightly-doped source and drain.

Abstract: An integrated circuit device includes insulated-gate field effect transistors employing a semiconductor gate electrode used as a logic element. Part of the input interconnection layer serves as the semiconductor gate electrode and orthogonally intersects with a conductive layer. The logic circuits are interconnected to constitute a random gate logic circuit that can be operated at high speeds and formed with a high density.

Abstract: A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connect to the nodes (26, 30) of the circuit (10). The reduced area butting contacts comprise vertically-disposed, doped polysilicon plugs (94), which intersect and electrically interconnect buried polysilicon layers (load poly 88, gate poly 52a) with doped silicon regions (80) in a bottom layer. Adding the processing steps of forming separate gate oxides for the pull-down and pass-gate transistors results in a smaller cell area and reduces the requirements of the contacts from three to two. Further, the separate gate oxidations permit independent optimization of the pull-down and pass-gate transistors.

Abstract: An electrically programmable and electrically erasable floating gate memory device which includes an integrally formed select device. In the n-channel embodiment, a boron region is formed adjacent to the drain region under the control gate and extends slightly under the floating gate. This region is formed using a spacer defined with an anisotropic etching step. The region, in addition to providing enhanced programming, prevents conduction when over-erasing has occurred, that is, when the erasing causes the cell to be depletion-like.

Abstract: A semiconductor integrated circuit (IC) comprises a functional block which includes a plurality or first and second power source wiring layers arranged parallel to one another and formed so as to extend in a predetermined direction. A plurality of element regions are located between adjacent pairs of the first and second power source wiring layers. A cell block on the (IC) includes a plurality of cell column areas each having third and fourth power source wiring layers which are arranged parallel to each other and formed so as to extend in the predetermined direction. An element region is located between the third and fourth power source wiring layers. A plurality of wiring regions are located between adjacent cell column areas.

Abstract: A field effect transistor having operating characteristics based on the control and modulation of the punch through phenomenon. The channel region between the source and the drain regions is appropriately doped such that the source and drain depletion regions overlap when no potential is applied between source and drain. The overlapped region in the absence of a gate field has a potential barrier. A gate voltage modulates the barrier to below the kT/q parameter. The source-to-drain fields also modulate the barrier.

Abstract: On a semiconductor substrate (14, 38) T-type undercut electrical contact structure (12, 36) and methodology provides a diffusion barrier (26, 40) preventing migration therethrough from a gold layer (30, 48) along the sides of an undercut schottky metal lower layer (28, 44) into the active region of the semiconductor substrate. In one embodiment, the diffusion barrier (26) is provided at the base of the gold layer (30). In another embodiment, the gold layer (48) is encapsulated by the diffusion barrier (40) on the bottom (46) and sides (56). The diffusion barrier base layer is deposited. The diffusion barrier side layers are electroplated.

Abstract: Disclosed is a digital computer having memory means stacked on an insulating layer over a semiconductor substrate. In one embodiment, the memory means includes an array of diodes which overflies the substrate and generates control signals for an arithmetic section that lies in the substrate; and in another embodiment, the memory means includes N arrays of diodes which overlie the substrate and operate in parallel to generate signals representing arithmetic transformation of a portion of their address inputs.

Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16). A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and an opposite-conductivity buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency. Connective regions (46) extend from the buried web to the upper semiconductor surface to contact electrical leads (54) typically arranged in a parallel pattern. The maximum dopant concentration in the intermediate cell regions occurs vertically within 20% of their mid-points.

Abstract: A bipolar transistor comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline Si layer formed on the insulation film. A p-type region formed in the convex portion serves as an intrinsic base region, the polycrystalline Si layer serves as an extrinsic base region, an n-type region formed in the intrinsic base region serves as an emitter region, and the body serves as a collector region.

Abstract: A semiconductor device provided with capacitors which have accurate and reliable capacitance ratio, is disclosed. The semiconductor device comprises first and second capacitors. The first and second capacitors have substantially the same physical configuration but they have different dielectric layers of different values of dielectric constant. Thus, a capacitance ratio of the first capacitor to the second capacitor is determined in accordance with the dielectric constant ratio of the dielectric layers thereof.

Abstract: The tunnelling area of a EEPROM memory device of the FLOTOX type is efficiently reduced in respect of the minimum areas obtained by means of current fabrication technologies, by forming the injection zone for the transfer of the electric charges by tunnel effect to an from the floating gate through an original self-aligned process, which allows to limit the dimensions of such a tunnelling area independently from the resolution limits of the available photolithographic technology.

Abstract: A lateral DMOS transistor includes a high conductivity substrate having an epitaxial layer grown thereon to have a resistivity suitable for the transistor body. A highly doped topside body contact is diffused into the epitaxial layer along with an abutting heavily doped source. The source is self-aligned with a conductive polysilicon gate lying on top of a thin gate oxide. After source diffusion the gate is oxide coated so as to be fully insulated. A main drain electrode portion is diffused near the opposing side of the gate spaced a distance away. A lightly doped drain region portion extends between the main drain region and the edge of the gate providing the required surface breakdown behavior. The main drain diffusion portion is extended into the epitaxial layer so that the spacing between the heavily doped substrate and the drain diffusion produces depletion region reach through at a voltage that is lower than the drain avalanche voltage. Several embodiments are set forth for practicing the invention.

Abstract: A semiconductor memory device comprises a semiconductor substrate, four memory cells arranged in point symmetry on the main surface, each of the memory cells having one transistor (6) formed around the point of symmetry and one capacitor adjacent to the outside of the transistor (6), the capacitor having a surface capacitor region (4a) parallel to the main surface and a trench capacitor region (40a) parallel to a side wall of a trench (40) formed in the main surface along the outer periphery of the surface capacitor region (4a), and an insulating layer (10) covering the memory cells and having one contact hole (2) arranged at the center of the point symmetry, with the contact hole (2) enabling electrical contact to each transistor (6).

Abstract: A hot electron transistor (HET) comprising features that can result in substantially improved device characteristics is disclosed. Among the features is a highly doped (typically more than about 10.sup.20 cm.sup.-3) thin base region, a thin (typically less than about 100 nm) collector depletion region, and a highly doped (typically more than about 10.sup.19 cm.sup.-3) collector contact region. Ballistic transport through the base region is possible, despite the high doping level, because the inelastic scattering rate can be relatively low in at least some highly doped compound semiconductors such as GaAs, AlGaAs, InGaAs, or InP. The elastic scattering rate in the base region can be relatively low if the dopant atoms have an appropriate non-random distribution. Techniques for achieving such a distribution are disclosed. Transistors according to the invention are expected to find advantageous use in applications that demand high speed, e.g., in repeaters in high capacity optical fiber transmission systems.