Abstract: A temperature sensor having a semiconductor body is disclosed. The semiconductor body includes a substrate of a compound semiconductor and an epitaxial layer of a mixed crystal in which different conduction band minima with different effective masses are energy-wise closely adjacent. A particular embodiment comprises the mixed crystal series gallium-aluminum-arsenic having the composition Ga.sub.1-x Al.sub.x As, in which the aluminum concentration is 0.2.ltoreq.x.ltoreq.0.43. The temperature sensor formed in this manner provides a simplified design and a wide linear temperature range. Additionally, the temperature range is extended without the need for a shunt resistance.

Abstract: A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor material, but the gate electrode does not extend over any sidewall of the silicon island. In order to electrically isolate the source and drain regions in the areas of the silicon island not subtended by the gate electrode, a pair of diodes in series is used to eliminate the shorting paths.

Abstract: A high electron mobility transistor (HEMT) structure, and a corresponding method for its fabrication, in which the maximum power output is increased by a factor of approximately two. The structure includes a stop etch layer, which is of aluminum arsenide in the disclosed embodiment, and which functions both to facilitate selective etching during fabrication and, because of its relatively wide band-gap, as a current confinement layer during operation. Since the current confinement action has a detrimental effect in the region of the source contact of the device, by tending to raise the source resistance and the threshold voltage at which current saturation occurs, this effect is avoided by aligning the source region with an edge of the gate electrode during fabrication, to minimize the source resistance and the threshold voltage for maximum current saturation.

Abstract: A method of fabricating a resistor in a polycrystalline semiconductor material includes rendering the material conductive by a heavy doping implantation of ions which are electrically active with respect to the material. Ions which are electrically inactive, for example, argon ions, are then implanted in an area of the material with a concentration that is controlled to form a resistor having a desired resistance value. The method permits the precise and accurate control of the fabrication of load resistors for logic circuits within a very wide resistance range, and the resulting resistance values are a linear function of the concentration of the inactive ions.

Abstract: An integrated circuit structure is made up of laterally spaced islands separated from each other by closed annular grooves of an electrically isolating matter which can be either ambient air or vacuum, or an oxide formed from the adjacent semiconductor material.

Abstract: A three-terminal quantum well device, which functions somewhat analogously to an MOS transistor. That is, the three terminals of the device can generally be considered as source, gate, and drain. An output contact is connected by tunneling to a number of parallel chains of quantum wells, each well being small enough that the energy levels in the well are quantized discretely. In each of these chains of wells, the second well is coupled to a common second conductor, and the first well is electronically coupled to a common first conductor.

Abstract: A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

Abstract: A semiconductor integrated-circuit apparatus includes an electro-conductive layer formed on a substrate, a plurality of internal cells formed on the electro-conductive layer, a plurality of bonding pads arranged around the internal cells, and a plurality of bias cells which are common to the plurality of internal cells and which generate a predetermined voltage. A plurality of bias buffer circuits supply the predetermined voltage generated in the bias cells to the internal cells.

Abstract: A radiation-emitting semiconductor device (i.e. an LED or laser) emits radiation produced by radiative recombination of electrons from a field induced two-dimensional (2-d) electron gas with holes from a field induced two-dimensional (2-d) hole gas. The device uses a narrower band semiconductor active layer sandwiched between two layers of a wider band semiconductor. Top and bottom gates are used to induce the electron and hole 2-d gasses in the active layer. N+ and P+ regions are used to contact the 2-d electron and hole gasses to provide separate biasing. The thickness of the active layer is such that a field induced PN junction or PIN structure is formed at which radiative recombination can occur.

Abstract: A semiconductor integrated resonant-tunneling device having multiple negative-resistance regions, and having essentially equal current peaks in such regions, is useful as a highly compact element, e.g., in apparatus designed for ternary logic operations, frequency multiplication, waveform scrambling, memory operation, parity-bit generation, and coaxial-line driving. The device can be made by layer deposition on a substrate and includes a resonant-tunneling structure between contacts such that side-by-side first and third contacts are on one side, and a second contact is on the opposite side of the resonant-tunneling structure.

Abstract: A vertical transistor device is characterized by active regions vertically separated by a narrower control region. The control region is defined by conducting layer extensions which extend into a groove within which semiconductor material is regrown during device fabrication. The device is further characterized by regions of isolating material, located horizontally adjacent to the active regions, said isolating material serving to reduce parasitic capacitance and improve thermal distribution within the device, thereby improving frequency and power performance.

Abstract: In a semiconductor integrated circuit device, input protective elements have current limiting resistors which are diffused resistors of a second conductivity type formed in a first semiconductor region of a first conductivity type isolated electrically by a second semiconductor region of the second conductivity type, with the first conductivity type semiconductor region being in a floating state electrically. The input protective elements create less leak current and have high electrostatic durability.

Abstract: A semiconductor monolithic integrated circuit comprising circuit elements built into isolated epitaxial layer islands is described. The isolation is accomplished by part by a p-n junction between the epitaxial layer and its substrate, in part by an insulated zone of converted epitaxial material sunken only part way through the layer, and in part by a depletion layer or buried zone of the substrate conductivity type.

Abstract: Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance anti-fuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath.

Abstract: A semiconductor device having a light transparent window includes: a wall produced at an outer contour of a light receiving section on the surface of a semiconductor chip, the molding resin which is produced after a process of inserting the chip in a metal mold. The wall and the metal mold adhere with each other for producing a space between the chip and the metal mold so that a light transparent window is produced at a light introduction section in a separate position from the wall above the chip.

Abstract: This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.

Abstract: An integrated circuit is disclosed in which a plurality of semiconductor substrates are stacked in such a manner that an insulating board, provided with (1) structure, such as grooves, for transmitting a coolant so as to dissipate heat, and (2) an electrical interconnection member for electrically connecting adjacent semiconductor substrates, is sandwiched between semiconductor substrates. In order to attain the high-speed signal transmission between a semiconductor substrate and an insulating board, a signal current flows not only in a main surface of the semiconductor substrate but also in directions perpendicular to the main surface. The insulating board may be formed of an insulating silicon carbide plate which has a plurality of grooves filled with a metal.

Abstract: A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages each including a 256-R resistor string DAC. The analog output voltage of the first stage is coupled to the second stage by two buffer amplifiers each formed by a non-epitaxial process using a P-type substrate. The amplifiers include NMOS and PMOS-cascoded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnections within the source.

Abstract: A rectifier is fabricated from a P-N junction having a P-type semiconductor layer and an adjacent N-type semiconductor layer. A mesa structure is formed in at least one of said layers. Impurities are deposited at the top of the mesa to form a high concentration region in the surface thereof. The impurities are diffused from the top surface of the mesa toward the P-N junction, whereby the mesa geometry causes the diffusion to take on a generally concave shape as it penetrates into the mesa. The distance between the perimeter of the high concentration region and the wafer substrate is therefore greater than the distance between the central portion of said region and the wafer substrate, providing improved breakdown voltage characteristics and a lower surface field. Breakdown voltage can be measured during device fabrication and precisely controlled by additional diffusions to drive the high concentration region to the required depth.

Abstract: Disclosed is a semiconductor device implementing a resistor-load level shift circuit which avoids high voltage crossings of PN junctions by utilization of a combined drain resistor region and a unique circuit layout.