Abstract: A semiconductor IC element is three-dimensionally structured with a first active layer formed on a single crystalline silicon substrate and a second active layer formed by melting polycrystalline silicon by irradiation on an insulative layer which electrically insulates it from the first layer. Each active layer is comprised of single crystalline areas where transistors may be formed and separation areas which insulate them. PMOS, NMOS or CMOS field effective transistors are formed on these active element areas. A test circuit for testing the originally intended functions of the element as well as its redundant circuits may be formed on these layers. Throughholes are provided to connect the vertically separated active layers.

Abstract: A semiconductor memory device comprises four memory cells (4a, 6) arranged in point symmetry on a semiconductor substrate (1), and an insulating layer (10) covering the memory cells and having one contact hole (2) placed in the center of the point symmetry, with the contact hole enabling electrical connection to each of the memory cells.

Abstract: An integrated circuit has integrated circuit cells drawn from a library. The cells are rectangular with input lines extending from both sides of the cell to a logic element on the cell and outputs taken from the logic element to both sides of the cell. Input and output lines terminate at connection points. Short linear lengths of conductors selectively interconnect the connection points across the boundary between adjacent cells. The arrangement permits on-cell series and parallel connection of cells.

Abstract: A semiconductor device, which is subjected to a thermal treatment process during manufacture of the device, includes a wafer having semiconductor regions insulated from a semiconductor substrate by insulation layers, with at least one semiconductor element formed in each of the semiconductor regions, and at least one semiconductor element formed in the semiconductor substrate. The main surface of the semiconductor regions are substantially in the same plane as the main surface of the semiconductor substrate. The total area of the main surfaces of the semiconductor regions is 30% or less of the area of the wafer to prevent warping of the wafer resulting from the thermal treatment process.

Abstract: The invention comprises a metal-oxide-semiconductor (MOS) capacitor formed on silicon carbide. By utilizing new techniques for obtaining single crystals and monocrystalline thin films of silicon carbide, and by positioning the ohmic contact and the metal contact on a common side of the silicon carbide semiconductor portion, devices are obtained which are commercially viable and which demonstrate reduced series resistance, lesser leakage current and greater capacitance than have previous devices formed on silicon carbide.

Abstract: A MESFET device includes a semi-insulative substrate, a source region, a drain region, a channel region, a source electrode, a drain electrode, a gate electrode, and a gate-electrode pad. The source region, drain region, and the channel region are formed in a surface region of the substrate. The three electrode and the gate-electrode pad are formed on the substrate. The MESFET device further comprises a conductive layer formed on the substrate and surrounds the source electrode and the gate-electrode pad. The conductive layer is connected to the drain electrode.

Abstract: An energy filter for carriers in semiconductor devices and devices with such filters are disclosed. The filter is a superlattice and the filtering action arises from the subbands and gaps in the conduction and valence bands of the superlattice. A heterojunction bipolar transistor with the filter between the emitter and base has carriers injected from the emitter into the base with energies confined to levels that minimize transit time across the base; a MESFET with a filter between a heterojunction source to channel has carriers injected with energies confined to minimize transit time across the channel. A diode with a filter in front of a drift region limits the spread of energies of injected carriers.

Abstract: A semiconductor device is provided which includes first and second semiconductor elements of different types stacked alternately. A plurality of cooling members are each disposed between the paired first and second semiconductor elements located adjacent to each other for cooling the semiconductor elements and electrically connecting the elements to each other. In other words, the cooling members will have one of the first semiconductor elements on one side and one of the second semiconductor elements on the other side. At least one connecting conductor is provided for connecting at least one of the first semiconductor elements and at least one of the second semiconductor elements in an anti-parallel connection and also for connecting a plurality of the anti-parallel connections in series to one another.

Abstract: A common island complementary-metal-oxide semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. Both N-channel and P-Channel transistors are formed in the common island of semiconductor material, but the gate electrode does not extend over the sidewalls of the silicon island. In order to electrically isolate the source and drain regions for each transistor, the areas of the silicon island outside of the channel region are doped with the appropriate dopants to form back-to-back diodes in series with respect to the source and drain regions. Additionally, a diode is disposed between both the N-channel and P-channel transistors to electrically isolate the two transistors.

Abstract: A hot-electron or hot-hole transistor includes a base region through which current flow is by hot majority charge carriers. The emitter-base barrier-forming means comprises a barrier region having a sufficiently large thickness and impurity concentration of the opposite conductivity type that the barrier region is at least over part of its thickness undepleted by the depletion layer or layers present at the emitter-base barrier at zero bias. The application of a bias voltage (V.sub.BE) between the base and emitter of the transistor is necessary to establish a supply of the hot majority carriers having energies above the base-collector barrier, and this improves the collection efficiency of the transistor. In one form the emitter-base barrier-forming means also comprises a Schottky contact. In another form the emitter comprises an ohmic contact. The supply of hot majority carriers may be established by avalanche or zener breakdown of the barrier region or by punch-through of the depletion layer(s).

Abstract: The inventive semiconductor integrated circuit device comprises a plurality of regularly disposed elementary units, each including a P channel MOS FET element paired with and an N channel MOS FET element. Desired ones of the elementary units each comprise a MOS field effect transistor having an ordinary form of a source-drain region formed by a diffusion region, while the remaining elementary units each have a diffusion region selectively connected to serve as a resistive element. Consequently, a desired circuit can be implemented without a resistive element being formed on each elementary unit.

Abstract: A high mobility p channel semiconductor device (such as a field-effect transistor) is suitable for operation at room temperature, for example in a circuit with an n channel device. Whereas hole modulation doping both in single heterojunction and in heterostructure quantum well devices provides a significant increase in hole mobility only at cryogenic temperatures, the present invention employs less than 5 nm wide and very deep quantum wells (about 0.4 eV and deeper) to reduce the effective mass of "heavy" conduction holes for motion in the plane of the quantum well. Hole mobilities at 300 degrees K. are obtained in excess of 2.5 times those in bulk material of the same narrow bandgap semiconductor as used for the quantum well. In a particular example such a quantum well is formed of GaAs (or GaInAs) between AlAs barrier layers.

Abstract: A previously ignored property of a degenerate 2-dimensional gas of charge carriers in a quantum well (to be termed the quantum-capacitance effect) makes possible a novel class of transistors. In these devices the collector (a quantum well having high transverse conductance) is located between gate and emitter, with a barrier layer between emitter and collector, and a relatively thin barrier layer between collector and gate, and the chemical compositions and/or thicknesses of the various layers are chosen such that application of a voltage to the gate results, as a manifestation of the quantum-capacitance effect, in an induced charge in the emitter, whereby a current between emitter and collector can be controlled by means of a voltage applied to the gate. Transistors according to the invention potentially are very fast. Exemplarily the invention is embodied in a GaAs/AlGaAs heterostructure.

Abstract: An environmental interface for a semiconductor electro-optical conversion device layer that is optically transparent, electrically conductive and chemically passivating, made of an elemental semiconductor with an indirect band gap>1 electron volt in a layer between 20 and 200 Angstroms thick. A GaAs covered by GaAlAs converter with a 100 Angstrom Si layer over the GaAlAs is illustrated.

Abstract: Testing of the gate oxides of all the transistors of a single die in a silicon wafer to be diced into a plurality of dice in a single operation is effected at an intermediate stage of the fabrication process by providing a metal layer contacting selectively each of the gate electrodes of a die at an intermediate stage of the processing and providing between the layer and the wafer a voltage of amplitude insufficient to cause significant tunneling current through good gate oxides but sufficient to cause significant tunneling current through defective gate oxides.

Abstract: A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high-performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carries in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads.

Abstract: A semiconductor integrated resonant-tunneling device having multiple negative-resistance regions, and having essentially equal current peaks in such regions, is useful as a highly compact element, e.g., in apparatus designed for ternary logic operations, frequency multiplication, waveform scrambling, memory operation, parity-bit generation, and coaxial-line driving. The device can be made by layer deposition on a substrate and includes a resonant-tunneling structure between contacts such that side-by-side first and third contacts are on one side, and a second contact is on the opposite side of the resonant-tunneling structure. Disclosed further are (two-terminal) resonant-tunneling diodes as incorporated in memory devices, e.g., in lieu of 2-transistsor flip-flops; room-temperature device operation; and devices comprising an essentially undoped accelerator region between an emitter contact and a resonant-tunneling structure.

Abstract: A gate array comprises a semiconductor substrate, a plurality of mutually parallel basic cell columns each made up of a plurality of basic cells formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions each formed between two mutually adjacent ones of the basic cell columns, and specific cells buried in one or a plurality of predetermined ones of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor and a second n-channel transistor which constitute a transmission gate.

Abstract: In a semiconductor component, which has various differently doped layers (2, 3, 4, 5) within a semiconductor substrate, an improvement of the electrical properties is achieved, wherein the thickness of the substrate in the current-carrying region is locally reduced by a deep etch well (10), the original mechanical stability of the semiconductor substrate largely remaining retained.

Abstract: In one embodiment a hot electron transistor uses lead telluride as the host crystal. The desired layers of increased band gap to provide the needed heterojunctions at the emitting and collecting junctions are realized either by substitution of europium and selenium in the host crystal or by superlattices of PbTe-CdTe. Variations described use either a tunneling barrier, graded barrier or camel diode barrier are used at the emitting junction. Other embodiments use a bismuth-antimony semiconductor alloy for one or more of the layers of the crystal.