Abstract: A method of forming shallow trench isolations is described. An etch stop layer is deposited on the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the etch stop layer into the semiconductor substrate to separate active areas. An oxide layer is deposited over the etch stop layer and within the isolation trenches wherein the oxide fills the isolation trenches and overlies the etch stop layer on the active areas. A polysilicon layer is deposited overlying the oxide layer within the isolation trenches and the oxide layer overlying the etch stop layer. The polysilicon layer is polished away until the oxide layer overlying the etch stop layer is exposed and the polysilicon layer remains only overlying the oxide layer in the isolation trenches. The polysilicon layer is oxidized whereby the oxidized polysilicon layer has a height close to the height of the oxide layer overlying the etch stop layer.

Abstract: An apparatus and method for gas-phase bromine trifluoride (BrF3) silicon isotropic room temperature etching system for both bulk and surface micromachining. The gas-phase BrF3 can be applied in a pulse mode and in a continuous flow mode. The etching rate in pulse mode is dependent on gas concentration, reaction pressure, pulse duration, pattern opening area and effective surface area.

Abstract: In a method for forming a device isolation region of an STI structure in a semiconductor device, a surface protecting oxide film is formed on the surface of a trench by a thermal oxidation. Thereafter, a first silicon oxide film is deposited on the whole surface to fill up the trench and to cover the silicon nitride film on the principal surface of the silicon substrate, and then, by using the silicon nitride film as a stopper, a first CMP process is carried so that the first silicon oxide film remains in the trench. Thereafter, the silicon nitride film is removed, and a HTO film is formed on the pad oxide film covering the principal surface of the silicon substrate. Then, a second silicon oxide film is formed, and furthermore, a second CMP process is carried out to the extent that the principal surface of the silicon substrate is not exposed. Finally, a wet etching is carried so that the device isolation region of the STI structure is formed with no deterioration of the electric characteristics.

Abstract: A micro-electro-mechanical structure including a semiconductor layer mounted to an annular support structure via an isolation layer wherein the semiconductor layer is micromachined to form a suspended body having a plurality of suspension projections extending from the body to the rim and groups of integral projections extending toward but spaced from the rim between said suspension projections. Each projection in said groups has a base attached to the body and a tip proximate the rim. The structure includes a plurality of inward projections extending from and supported on the rim and toward the body. Each such projection has a base attached to the rim and a tip proximate the body; wherein the grouped projections and the inward projections are arranged in an interdigitated fashion to define a plurality of proximate projection pairs independent of the suspension elements such that a primary capacitive gap is defined between the projections of each projection pair.

Abstract: Improved methods, compositions and structures formed therefrom are provided that allow for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer. In one such embodiment, improved methods, compositions and structures formed therefrom for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer are used in conjunction with high modulus polyurethane pads. In one embodiment, improved methods, compositions and structures formed therefrom are provided that reduce rough interlayer dielectric (ILD) conditions for a wafer during CMP processing of such a wafer. Accordingly, this reduction of rough ILD reduces “chatter scratches” which are scratches that emanate from regions of a wafer that has undergone CMP processing. Advantageously, reduction in “chatter scratching” reduces cracking (i.e., “wormholing”) in layers of the wafer that have been planarized.

Abstract: A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form.

Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically the oxide is selected from silicon oxide, silicon oxynitride, tantalum oxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) of chemical vapor deposition (CVD).

Abstract: The present invention provides a method of making self-aligned bit-lines on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a plurality of word-lines located on the silicon substrate and a first dielectric layer that covers each word-line. A plurality of bit-line contacts are formed that are level with the surface of the first dielectric layer. A second dielectric layer is formed on the surface of the semiconductor wafer and a plurality of node contacts are formed in the second and first dielectric layer, which are leveled with the surface of the second dielectric layer. Portions of the second dielectric layer are removed to make the top portion of each node contact higher than the surface of the second dielectric layer. A spacer is formed around this top portion of each node contact.

Abstract: A system and method for identifying events in a manufacturing process from a sequence of m-dimensional input data signals, m≧2 obtained from monitoring of the manufacturing process utilizing a data processor for transforming each m-dimensional input data signal to a set of output data signals based on an orthogonal polynomial transform function, wherein the input data signals are used as coefficients in evaluating the polynomial transform functions. The data processor also integrates the transform function within the defined limits of the transform function to determine a scalar value as a function of time. A display system may be used to display a graph of the scalar values as a function of time for visually identifying events or the processor may identify events based on detected scalar values. The transform function may be Fourier, Chebyshev, Legendre or other polynomial type function.

Abstract: A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.

Abstract: A technique is provided for laying out vias between metal layers in an integrated circuit structure utilizing conventional Metal n and Metal N+1 databases. A first database (Metal n) is created that defines a lower conductive layer. A second database (Metal N+1) is created that defines an upper conductive layer. Selected intersections of the first database and the second database are then determined, thereby creating a third database (via n) that defines a pattern of vias between the lower conductive layer and the upper conductive layer. This allows interconnect vias to be optimized in size and shape, thus providing lowest possible interlayer resistance, which in turn provides the best possible circuit performance and reliability.

Abstract: A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).

Abstract: Disclosed is a manufacturable silicon-based modular integrated circuit structure having performance characteristics comparable to high frequency GaAs-based integrated circuit structures, comprising materials and made in process steps which are compatible with existing low cost silicon-based integrated circuit processing.

Abstract: In-laid metallization patterns of copper or a copper alloy are fabricated by a damascene-type process wherein the upper surface of a thick, electroplated copper or copper alloy blanket or overburden layer filling recesses in a substrate surface is subjected to a mask-less, chemically-based differential etching step for partially planarizing/thickness reduction prior to a step of planarization by chemical-mechanical polishing (CMP). The inventive process enables an increase in manufacturing throughput, reduction in cost, and reduction in spent CMP slurry generation.

Abstract: A method for fabricating a field oxide layer capable of being applied to highly integrated circuits. The semiconductor device according to the present invention prevents electric field concentration at the corners of the active region, by filling a recess generated in a field oxide layer with an additional oxide spacer. The method includes the steps of a) forming a trench in a semiconductor substrate; b) forming an insulating layer on the resulting structure and burying the trench; c) forming a field oxide layer by controlling topology of the insulating layer in a wet etching process, wherein the wet etching process forms a recess at a corner of the field oxide layer so that a portion of sidewalls of the active region is exposed; d) forming an additional field oxide spacer layer at the recess in order to bury the exposed sidewall portion of the active region; and e) vertically growing an epitaxial layer on the exposed active region.

Abstract: A chamber 28 comprises a radiation source 58 capable of emitting radiation having a wavelength that is substantially absorbed in a predetermined pathlength in a thickness of a layer 22 on a substrate, and a radiation detector 62 adapted to detect the radiation. The radiation is substantially absorbed in a first thickness of the layer 22, and after at least partial processing of the layer 22, is at least partially transmitted through a second thickness of the layer 22 and reflected by one or more underlayers 24 of the substrate 20.

Abstract: A method including introducing a focus ion beam and an interactive species to a metal material on a substrate within a processing chamber and etching the metal material.

Abstract: A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners.

Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.

Abstract: Disclosed is a copper-based metal polishing solution which hardly dissolves a Cu film or a Cu alloy film when the film is dipped into the solution, and has a dissolution velocity during polishing several times higher than that during dipping. This copper-based metal polishing solution contains at least one organic acid selected from aminoacetic acid and amidosulfuric aminosulfuric acid, an oxidizer, and water.