Abstract: A method for fabricating a capacitor of a semiconductor device is provided. In the capacitor fabricating method, the step of forming a lower electrode by using gas including chlorine is included after the step of forming hemispherical grained silicon (HSG—Si) seeds. Also, after the step of selectively growing only HSG—Si seeds formed on the lower electrode, the step of removing the HSG—Si seeds formed on an insulation layer pattern through an etching process using a gas including chlorine is included. Thus, the surface area of the lower electrode is increased, so that capacitance is increased. Also, an electrical short between the lower electrodes of each adjacent capacitor can be prevented without decreasing capacitance.

Abstract: The invention concerns a method for simultaneously forming a metallization and contact structure in an integrated circuit. The method involves the steps of etching a trench dielectric layer of a composite structure having a semiconductor substrate with an active region, a gate structure thereon, at least one dielectric spacer adjacent to the gate structure, a contact dielectric layer over the semiconductor substrate, the gate structure and the dielectric spacer, an etch stop layer over the contact dielectric layer, and a trench dielectric layer over the etch stop layer, to form a trench in the trench dielectric under etch conditions which do not substantially etch the etch stop layer; thereafter, forming an opening in the etch stop layer and the contact dielectric layer by etching under conditions which do not damage the gate structure to expose the active region; and depositing a conductive material into the opening and the trench.

Abstract: The process comprises: etching, in a semiconductor substrate (2), at least one trench (3) with predetermined width and depth; depositing, on the substrate and in the trench, a stack of successive and alternate layers of Si1−xGex (0<x≦1) and Si (5-8), the number and the thickness of which depend on the final use intended for the heterostructure; and chemical-mechanical polishing in order to obtain a final heterostructure having a plane upper main surface, level with which the stack layers deposited in the trench are flush.

Abstract: A semiconductor substrate processing chamber provides a bi-directional process gas flow for deposition or etching processes. The bi-directional gas flow provides uniformity of deposition layer thickness or uniformity of etching without the need to rotate the substrate. Junctions are provided at opposite ends of a processing chamber. Inlet and outlet ports are provided on each junction. Inlet and outlet ports on opposite junctions cooperate to provide a gas flow in a first direction for half of the process cycle, and in a second direction for the other half of the process cycle.

Abstract: A machine for etching the edge of a wafer comprising a rotating holding plate having a work platform, the work platform having a first fillister for spraying gas to maintain a certain distance between the work platform and the wafer, a second fillister set around the periphery of the first fillister for reducing pressure of the sprayed gas at the edge of the wafer, and a plurality of holding pins; a vacuum manipulator; and an etching solution leading apparatus.

Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

Abstract: A process for revealing agglomerated intrinsic point defects in a single crystal silicon sample. The process includes heat-treating the single crystal silicon sample, cooling the heat-treated sample and then coating a surface of the cooled sample with a composition containing a metal which is capable of decorating agglomerated intrinsic point defects. The coated sample is then heat-treated in an inert atmosphere at a temperature and for a time sufficient to diffuse the metal into the sample. A non-defect delineating etch is performed, followed by a defect delineating etch to reveal the decorated agglomerated intrinsic point defects.

Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

Abstract: A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma.

Abstract: A planarization process in which an organic film prevents oxide dishing during the chemical mechanical polishing step. In the planarization process an organic film having high CMP selectivity to silicon dioxide is spun over silicon dioxide. A patterned mask is then placed over the organic film and the exposed portions of the organic film are etched away. The remaining portions of the organic film prevent oxide dishing during chemical mechanical polishing because the high CMP selectivity of the organic film to silicon dioxide stops the etching before oxide dishing occurs. The organic film may then be oxygen ashed off the planarized surface if so desired.

Abstract: A dry etching method is disclosed for use in patterning a stacked film of a metal film containing aluminum as the base component and a thin film including at least one of titanium and titanium nitride. In this method, the thin film is dry-etched using a first etching gas (a mixture of CF4 gas, Ar gas and Cl gas) having a gas composition for preventing the metal film from being processed. The metal film is then dry-etched using a second etching gas (a mixture of Cl gas and BCl3 gas) having a gas composition other than the first etching gas.

Abstract: A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a fixed abrasive polishing pad while maintaining the pH of a planarizing liquid adjacent the polishing pad at an approximately constant level by buffering the planarizing liquid. The planarizing liquid can include ammonium hydroxide and ammonium acetate, ammonium citrate, or potassium hydrogen phthalate. In another embodiment, the planarizing liquid can have an initially high pH that has a reduced tendency to decrease during planarization. The planarizing liquid can also include agents, such as isopropyl alcohol, ammonium acetate or polyoxy ethylene ether that can increase the wetted surface area of the microelectronic substrate and/or reduce drag force imparted to the microelectronic substrate by the polishing pad.

Abstract: The present disclosure relates to semiconductor processing, and to the plasma etching of organic layers, and in particular antireflective coating layers. We have discovered a particular combination of gases useful in producing chemically reactive plasma species, which provides unexpected control over etched feature critical dimension, etch profile, and uniformity of etch across a substrate surface, despite a difference in the spacing of etched features over the substrate surface. The combination of gases which produces chemically reactive plasma species consists essentially of CxHyFz, a bromine-comprising compound (which is typically HBr), and O2, where x ranges from 1 to 4, y ranges from 0 to 3, and z ranges from 1 to 10. Oxygen atoms may be substituted for hydrogen atoms in the CxHyFz compound to a limited extent Essentially inert gases which do not produce chemically reactive species may be added to the combination of etchant-species producing gases.

Abstract: A method for monitoring the performance of a material removal tool includes providing a wafer having at least one process layer formed thereon; measuring the thickness of the process layer; removing at least a portion of the process layer in the material removal tool until an endpoint of the removal process is reached; determining a removal rate based on the measured thickness of the process layer and a duration of the removal process until the endpoint is reached; and comparing the determined removal rate to an expected removal rate to monitor the performance of the material removal tool. A processing line includes a metrology tool, a material removal tool, and a process controller. The metrology tool is adapted to measure a thickness of a process layer formed on a wafer. The material removal tool is adapted to remove at least a portion of the process layer until an endpoint is reached.

Abstract: A given planarity of the underlying layer is ensured after removal of a porous layer. In the first step, a porous layer is filled with a preprocess solution (e.g., water). In the second step, the preprocess solution filling the porous layer is replaced with an etchant (e.g., fluoric acid), and the porous layer is etched by the etchant. With this process, the time in which the porous layer is filled with the etchant is shortened to suppress variations in progress of etching.

Abstract: A new method is provided for the creation of a fuse. A layer of metal is first deposited, the layer of metal is patterned and etched creating a metal strip that is interrupted by a gap. The fusing function is created in the gap, the interrupted metal strip serves as the connectors to the fuse. A layer of conducting conjugated polymer is deposited over the metal strip and the therein created gap, the polymer is etched back leaving the deposited polymer in the gap between the two metal strips.

Abstract: The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.

Abstract: The invention includes methods of forming memory circuitry, including methods of forming memory circuitry comprising a buried bit line array of memory cells. In one implementation, a method of forming memory circuitry comprising a buried bit line array of memory cells includes, in a single planarizing step, planarizing storage node contact opening plugging material and bit line trench plugging material to insulating material to form bit lines and storage node contacts which are electrically isolated laterally from one another by the insulating material. In one implementation, a method of forming memory circuitry comprising a buried bit line array of memory cells, includes forming word lines over a semiconductor substrate. An insulating layer is formed over the substrate and over the word lines. Using a single photomasking step, bit line contact openings and capacitor storage node contact openings are patterned and formed into the insulating layer.

Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

Abstract: An improved dry plasma cleaning process for the removal of native oxides, or other oxide films or growth residue, from openings formed in an insulating layer provided over a semiconductor substrate, without damaging the substrate or significantly affecting the critical dimension of the opening is disclosed. A mixture of nitrogen trifluoride (NF3), ammonia (NH3) and oxygen (O2) is first injected upstream into a microwave plasma source and is exited, and then the plasma is flowed downstream from the plasma source into a reaction chamber containing the substrate.