Abstract: A method for forming a multi-level metal interconnection, comprising the step of forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.

Abstract: A dual damascene type of structure of vias and trenches formed using layers of low k dielectric material is disclosed, and a process for making same without damage to the low k dielectric material during removal of photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings in the layers of low k dielectric material. Damage to the low k dielectric material is avoided by forming a first layer of low k dielectric material on an integrated circuit structure; forming a first hard mask layer over the first layer of low k dielectric material; forming over the first hard mask layer a first photoresist mask having a pattern of via openings therein; and then etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein, using an etch system which will also remove the first photoresist mask.

Abstract: In a method for patterning a target material on a semiconductor substrate, a first hardmask material is deposited on the target material and a second hardmask material is deposited on the first hardmask material. The first hardmask material is different from the target material, and the second hardmask material is different from the first hardmask material. A patterned structure of a patterning material such a photoresist material is formed on the second hardmask material. Any exposed region of the second hardmask material is etched such that a second hardmask structure is formed from the second hardmask material remaining under the patterned structure. The etching reactant for etching the second hardmask material to form the second hardmask structure substantially does not etch the first hardmask material. The second hardmask structure is trimmed to reduce the length at each side of the second hardmask structure.

Abstract: There is provided a semiconductor device manufacturing method that comprises a first step of loading a processed substrate in a reaction chamber, a second step of introducing a reaction gas into the reaction chamber at a predetermined flow rate, a third step of maintaining an interior of the reaction chamber at a predetermined pressure, a fourth step of starting generation of plasma by supplying a high frequency power to an electrode arranged in the reaction chamber, a fifth step of applying a predetermined process to the processed substrate, and a sixth step of stopping generation of the plasma by stopping supply of the high frequency power after the predetermined process is completed, wherein the reaction gas is introduced continuously when the generation of the plasma is stopped.

Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

Abstract: A method for removing an iridium- and/or rhodium-containing material from a substrate, such as a semiconductor-based substrate, is provided. The method includes providing a substrate having an exposed iridium- and/or rhodium-containing material and exposing the substrate to a composition that includes at least one halogen-containing gas, whereby at least a portion of the exposed iridium- and/or rhodium-containing material is removed from the substrate.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.

Abstract: In method for manufacturing a silicon single crystal in accordance with a Czochralski method, during the growth of the silicon single crystal, pulling is performed such that a solid-liquid interface in the crystal, excluding a peripheral 5 mm-width portion, exists within a range of an average vertical position of the solid-liquid interface ±5 mm. There is also disclosed a method for manufacturing a silicon single crystal in accordance with the Czochralski method, wherein during the growth of a silicon single crystal, a furnace temperature is controlled such that a temperature gradient difference &Dgr;G (=Ge−Gc) is not greater than 5° C./cm, where Ge is a temperature gradient (° C./cm) at a peripheral portion of the crystal, and Gc is a temperature gradient (° C./cm) at a central portion of the crystal, both in an in-crystal descending temperature zone between 1420° C. and 1350° C. or between a melting point of silicon and 1400° C.

Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.

Abstract: A composition for mechanical chemical polishing of a layer in an insulating material based on a polymer with a low dielectric constant, comprising an acid aqueous suspension of cationized colloidal silica containing individualized colloidal silica particles not linked to each other by siloxane bonds and water as the suspension medium, process for mechanical chemical polishing of a layer of insulating material based on a polymer with a low dielectric constant and abrasive for the mechanical chemical polishing of a layer of insulating material based on a polymer with a low dielectric constant.

Abstract: Aspects for performing decapsulation of multi-chip devices are presented. One aspect includes removing a top die of the multi-chip device without employing a wet chemical etch and removing residual attach and package materials to expose a bottom die of the multi-chip device. An alternate aspect includes utilizing mechanical polishing and wet chemical etching to remove a top die of the multi-chip device, and exposing a bottom die through chemical decapsulation to allow failure analysis of the bottom die. A Flash memory die as a top die and a static random access memory (SRAM) die as a bottom die are included as a multi-chip device capable of decapsulation through these aspects.

Abstract: In the manufacture of a micromechanical device, a substrate, having a mask thereon, is etched using a flourine-containing etchant gas or vapour in the absence of a plasma through an opening in the mask to a desired depth to form a trench having a side wall and a base in the substrate. A layer of protecting substance is deposited on the exposed surfaces of the substrate and mask, and the protecting substance is then selectively removed from the base. The base is then etched using the fluorine-containing etchant.

Abstract: There is provided a method used for processing an organic low dielectric constant insulating film to a desired shape for enabling facilitated stripping of an organic film formed on top of the organic low dielectric constant insulating film. Specifically, there is provided a method for stripping an organic film formed on a layered unit having at least an organic low dielectric constant insulating film. This method includes generating radicals in a gas mainly composed of fluorine-based gas, and stripping the organic film by the generated radicals.

Abstract: A method of forming a pattern in a layer of material on a substrate, comprising providing a plurality of spheres, covering the layer on the substrate with the plurality of spheres to form a mask, reducing the diameter of at least one sphere of the plurality of spheres, etching the layer on the substrate using the at least one sphere having a reduced diameter as a mask, and etching the substrate.

Abstract: A method of anisotropically etching metals, especially iridium, platinum, ruthenium, osmium, and rhenium using a non-chlorofluorocarbon, fluorine-based chemistry. A substrate having metal deposited thereon, is inserted into an ECR plasma etch chamber and heated. A fluorine containing gas, such as, carbon tetrafluoride (CF4), nitrogen trifluoride (NF3) or sulfur hexafluoride (SF6) is introduced into the chamber and ionized to form a plasma. Fluorine ions within the plasma strike, or contact, the metal to form volatile metal-fluorine compounds. The metal-fluorine compounds are exhausted away from the substrate to reduce, or eliminate, redeposition of etch reactants.

Abstract: In a dry etching apparatus, a susceptor cover is attached to a substrate susceptor to shape it into a tapered contour, and no other element is positioned around a wafer support plane to ensure a flatness. A wafer positioning mechanism is provided near the perimeter of the wafer support plane, and it is raised to extend to a level higher than the wafer support plane and used in this status only upon setting or removing the wafer.

Abstract: A small, light-weight and highly maintainable etching system and an etching method for etching a large substrate with a homogeneous etching rate are provided. The etching system comprises an agitating electric field system disposed around the substrate, an agitating power source of high frequency, medium frequency or low frequency, agitating electrodes, amplifiers and a phase controller to agitate electrons or ions to increase the etching speed and the uniformity of the etching rate by promoting activation of reactive gas and uniformalizing a plasma density.

Abstract: A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask.

Abstract: SOI substrates are fabricated with sufficient quality and with good reproducibility. At the same time, conservation of resources and reduction of cost are realized by reuse of the wafer and the like. Carried out to achieve the above are a step of bonding a principal surface of a first substrate to a principal surface of a second substrate, the first substrate being a Si substrate in which at least one layer of non-porous thin film is formed through a porous Si layer, a step of exposing the porous Si layer in a side surface of a bonding substrate comprised of the first substrate and the second substrate, a step of dividing the porous Si layer by oxidizing the bonding substrate, and a step of removing the porous Si and oxidized porous Si layer on the second substrate separated by the division of the porous Si layer.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.