Patents Examined by Xiaoliang Chen
  • Patent number: 11027856
    Abstract: Multifunctional surfacing materials for use in composite structures are disclosed. According to one embodiment, the surfacing material includes (a) a stiffening layer, (b) a curable resin layer, (c) a conductive layer, and (d) a nonwoven layer, wherein the stiffening layer (a) and the nonwoven layer (d) are outermost layers, and the exposed surfaces of the outermost layers are substantially tack-free at room temperature (20° C. to 25° C.). The conductive layer may be interposed between the curable resin layer and the stiffening layer or embedded in the curable resin layer. According to another embodiment, the surfacing material includes a fluid barrier film between two curable resin layers. The surfacing materials may be in the form of a continuous or elongated tape that is suitable for automated placement.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 8, 2021
    Assignee: CYTEC INDUSTRIES INC.
    Inventors: Junjie Jeffrey Sang, Dalip Kumar Kohli, Kevin R. Mullery
  • Patent number: 11032915
    Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: June 8, 2021
    Assignee: RICHVIEW ELECTRONICS CO., LTD.
    Inventors: Siping Bai, Xianglan Wu, Zhijian Wang, Zhigang Yang, Jinqiang Zhang
  • Patent number: 11032901
    Abstract: Provided is a printed circuit board including: a first flexible insulating layer; a first rigid insulating layer stacked on a first portion of the first flexible insulating layer; and an electronic element embedded in the first flexible insulating layer in stacked formation with the rigid insulating layer.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jung-Hwan Park
  • Patent number: 11026326
    Abstract: A printed circuit board (PCB) structure and mounting assembly for joining two PCBs. A first PCB has a top and bottom surface faces and a peripheral end face separating the top and bottom surface. The first PCB has one or more conductive wire ends exposed at a surface of the peripheral end face; the exposed conductive wire ends forming multiple separate electrical contacts across the thickness and length of the PEF surface. A second PCB has a top surface face and one or more conductive pads exposed at the top surface at locations corresponding to locations of the multiple electrical contacts. A surface mount solder material is disposed on one or more exposed conductive pads for electrically connecting with corresponding the multiple electrical contacts. The disposed solder material stably joins the PEF surface of the first PCB to the top surface of the second PCB in a relative perpendicular orientation.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Todd E. Takken, Xin Zhang, Yuan Yao, Andrew Ferencz
  • Patent number: 11018452
    Abstract: A positioning fastener includes a base having a seat plate extended therefrom, a fixing portion disposed below the base for fastening to an electronic substrate, and an elastic positioning structure disposed above the base and including an urging plate, a pressing plate connected to the urging plate, a positioning space defined therein and a positioning member disposed at a bottom side thereof. The urging plate and the pressing plate are squeezed backwards and elastically deformed by a circuit board that is rotated downward so that the circuit board passes the urging plate and moves into the positioning space of the elastic positioning structure and a suspended board edge of the circuit board is secured in position by the positioning member. The pressing plate can be pressed by an external force to lift the urging plate, allowing the circuit board to be rotated in direction away from the positioning member.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 25, 2021
    Assignee: HANWIT PRECISION INDUSTRIES LTD.
    Inventors: Ming-De Wu, Ching-Kai Chang
  • Patent number: 11013109
    Abstract: A display unit includes a display panel, a circuit board bent from a front surface of the display panel toward a rear surface of the display panel, a window disposed on the front surface of the display panel to cover an active area, and a cover panel film disposed on the rear surface of the display panel and disposed between the display panel and the circuit board. The cover panel film includes a first portion overlapping with the display panel, and a second portion extending from the first portion to protrude from the display panel when viewed in a plan view. The second portion is disposed between the circuit board and the window when viewed in a cross-sectional view.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 18, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-Soo Han, Hwa-Su Lim
  • Patent number: 11013130
    Abstract: A display device includes a display panel including a display area on which a plurality of display elements is disposed and a non-display area on which one or more wires for driving the plurality of display elements are disposed. A back cover is attached to one surface of the display panel and has a plurality of openings. A roller unit winds or unwinds the back cover and the display panel, and a lifting unit moves the back cover and the display panel in a vertical direction. The plurality of openings overlaps the display panel, and each of the plurality of openings is disposed to be staggered with one or more of the openings in an adjacent row. A size of the back cover is larger than a size of the display panel.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 18, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Mi-Na Shin, ChounSung Kang, SunBok Song, GeunChang Park, Moonsun Lee
  • Patent number: 11013116
    Abstract: A flexible assembly for a display device and the display device are provided. The flexible assembly includes a flexible substrate, and a first output pad, a second output pad, a third output pad and a fourth output pad that are arranged on the substrate. The first output pad, the second output pad, the third output pad and the fourth output pad are sequentially arranged along a first direction and are spaced apart from each other. A pitch is between each output pad and an adjacent output pad, and the pitch is a sum of a spacing distance between each output pad and the adjacent output pad and a width of the adjacent output pad in the first direction. The pitch between the first output pad and the adjacent second output pad is smaller than the pitch between the third output pad and the adjacent fourth output pad.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 18, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liqiang Chen, Paoming Tsai, Weifeng Zhou, Chen Xu, Jifeng Tan
  • Patent number: 11006521
    Abstract: Provided are a wiring base plate and the like including an insulating substrate including a first surface portion including an aluminum oxide-based sintered body and a mullite-based sintered body; and a metallization layer including a second surface portion, the second surface portion containing at least one of a manganese compound and a molybdenum compound and being in contact with the first surface portion of the insulating substrate; wherein the second surface portion of the metallization layer and the first surface portion of the insulating substrate contain at least one of a manganese silicate phase and a magnesium silicate phase.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 11, 2021
    Assignee: KYOCERA Corporation
    Inventors: Isamu Kirikihira, Makoto Yamamoto
  • Patent number: 11006527
    Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baleegh Abdo, Nicholas T. Bronn, Oblesh Jinka, Salvatore B. Olivadese
  • Patent number: 10999929
    Abstract: The present disclosure describes expansion card interfaces for a printed circuit board and methods of making the same. The methods include forming electrical pads of the expansion card interface on a substrate, and dividing at least one electrical pad into a first portion and a second portion. The resulting expansion card interfaces have the first portion conductively coupled to a circuit on the printed circuit board, and the second portion conductively isolated from the first portion.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 4, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Che-Wei Chang, Cheng-Hsien Lee
  • Patent number: 10993314
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: April 27, 2021
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 10984957
    Abstract: A capacitor comprises a housing and a first stack of parallel plates within the housing. A first plate and a second plate in the first stack are capacitively coupled. The capacitor comprises a second stack of parallel plates within the housing. A third plate and a fourth plate in the stack are capacitively coupled. The capacitor also comprises a first input electrode and a second input electrode. The capacitor also comprises a first output electrode and a second output electrode on a side surface of the capacitor. The capacitor also comprises a dielectric material located between each plate in the first stack and the second stack. The first stack is not capacitively coupled with the second stack.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Samuel R. Connor, Stuart Brett Benefield, Matthew Doyle
  • Patent number: 10980127
    Abstract: A method is provided for forming a printed circuit board (PCB) assembly. The method may include drilling a first plurality of vias having a first diameter in a PCB and filling the first plurality of vias to form a first plurality of plated or filled vias. The method may also include drilling a second plurality of vias having a second diameter in the PCB, and filling the second plurality of vias to form a second plurality of plated or filled vias. The first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias such that the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 13, 2021
    Assignee: TTM Technologies Inc.
    Inventors: Michael Len, Chong Mei, Michael Lugert, Raj Kumar
  • Patent number: 10980129
    Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur, Wei-Lun Kane Jen, Sriram Srinivasan
  • Patent number: 10980119
    Abstract: A display device and a method of manufacturing the display device are capable of substantially minimizing damage to a display panel. The display device includes: a first substrate including a display area and a pad area; a polarization film disposed at an upper surface of the first substrate to overlap the display area; a flexible printed circuit board disposed at a lower surface of the first substrate; a via hole defined through the first substrate at the pad area; and a connection metal located at the via hole. The connection metal includes a connection portion disposed in the via hole and a first protruding portion that protrudes with respect to the first substrate, and the polarization film is spaced apart from the via hole in a plan view.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junwoo You, Atsushi Nemoto, Byoungdae Ye, Taeho Lee
  • Patent number: 10973135
    Abstract: A display device includes a display panel including a display area on which a plurality of display elements is disposed and a non-display area on which one or more wires for driving the plurality of display elements are disposed. A back cover is attached to one surface of the display panel and has a plurality of openings. A roller unit winds or unwinds the back cover and the display panel, and a lifting unit moves the back cover and the display panel in a vertical direction. The plurality of openings overlaps the display panel, and each of the plurality of openings is disposed to be staggered with one or more of the openings in an adjacent row. A size of the back cover is larger than a size of the display panel.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 6, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Mi-Na Shin, ChounSung Kang, SunBok Song, GeunChang Park, Moonsun Lee
  • Patent number: 10973116
    Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Khang Choong Yong, Ramaswamy Parthasarathy
  • Patent number: 10964474
    Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 30, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro Matsuo, Susumu Obata, Mitsuo Sano, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 10966324
    Abstract: A wiring board, a multilayer wiring board, and a method of manufacturing a wiring board adapted to make the filling of through holes and the formation of fine wiring patterns. The wiring board comprises an insulator; a through hole between front and back surfaces of the insulator; a through hole conductor for electrically connecting front and back surface side openings; through hole lands around the front and the back surface side openings, and connected to the through hole conductor; lid plating conductors on the front and the back surface sides, and placed on the respective through hole lands; and wiring patterns formed on the front are compatible and the back surface of the insulator. The thickness of the through hole lands is 1.0 ?m or more and 10.0 ?m or less, and the area of each lid plating conductor is less than the area of each through hole land.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 30, 2021
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Yasuyuki Hitsuoka