Patents Examined by Xiaoliang Chen
  • Patent number: 12254803
    Abstract: A display device is provided. The display device comprises a display panel including a plurality of signal pads and one or more dummy pads, and at least one flexible wiring board providing signals to the signal pads, wherein a maximum bias period of signals provided to a pair of adjacent signal pads with at least one dummy pad interposed therebetween is longer than a maximum bias period of signals provided to a pair of adjacent signal pads with no dummy pad disposed therebetween.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: March 18, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae Hoon Kwon, Ji Hyun Ka, Byung Sun Kim, Yang Wan Kim, Hyung Jun Park, Su Jin Lee, Jae Yong Lee, Jin Tae Jeong, Seung Ji Cha
  • Patent number: 12250768
    Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation b
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: March 11, 2025
    Assignee: DexCom, Inc.
    Inventors: Sean Frick, Louis Jung, David Lari
  • Patent number: 12238863
    Abstract: An electronic device is provided. The electronic device includes a substrate structure, a control unit, a first circuit structure, and an electronic unit. The substrate structure has a conductive via pattern and a dummy via pattern. The control unit is electrically connected to the conductive via pattern. The first circuit structure is electrically connected to the conductive via pattern. The electronic unit is electrically connected to the control unit through the first circuit structure. The dummy via pattern is electrically insulated from the first circuit structure.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: February 25, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Cheng-Chi Wang, Kuan-Feng Lee, Jui-Jen Yueh
  • Patent number: 12232266
    Abstract: A connection method for a chip and a circuit board includes: placing the circuit board on the chip, the circuit board having a first surface in contact with the chip having a plurality of contacts, and the circuit board having a plurality of through holes aligned with the plurality of contacts respectively; placing a mask on a second surface of the circuit board, the mask having a plurality of openings aligned with the plurality of through holes respectively; covering a surface of the mask with a conductive adhesive to fill the plurality of through holes with the conductive adhesive; and keeping portions of the conductive adhesive that are respectively in the plurality of through holes to be spaced apart from each other. The portions of the conductive adhesive that fill the plurality of through holes remain to provide an electrical connection between the circuit board and the chip.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: February 18, 2025
    Assignee: INTELLIMICRO MEDICAL CO., LTD.
    Inventors: Yu-chong Tai, Changlin Pang, Xihua Xia
  • Patent number: 12232265
    Abstract: A semiconductor storage device includes: a printed circuit board; a nonvolatile memory disposed on the printed circuit board; a memory controller disposed on the printed circuit board and configured to operatively control the nonvolatile memory; a capacitor disposed on the printed circuit board and configured to supply power to the nonvolatile memory and the memory controller; and at least one holder that holds the capacitor at an end portion of the printed circuit board. The holder includes a connecting portion connected to the end portion of the printed circuit board, and a pair of arm portions extending from the connecting portion toward an outside of the printed circuit board and configured to sandwich a body portion of the capacitor from both sides in a thickness direction of the printed circuit board.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: February 18, 2025
    Assignee: KIOXIA CORPORATION
    Inventor: Koji Ueno
  • Patent number: 12232256
    Abstract: A flexible hybrid electronic substrate and electronic textile including the same are provided. The flexible hybrid electronic substrate includes a first region and a second region. There is a joint between the first region and the second region. Each of the first region and the second region includes at least one selected from the group consisting of the following structure features: multilayer structure feature, anisotropic structure feature and pre-strained structure feature.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 18, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: I-Hung Chiang, Hung-Hsien Ko, Min-Hsiung Liang, Te-Hsun Lin, Chen-Tsai Yang, Hao-Wei Yu
  • Patent number: 12224103
    Abstract: An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 11, 2025
    Assignee: Intel Corporation
    Inventors: Brandon Marin, Jeremy Ecton, Suddhasattwa Nad, Matthew Tingey, Ravindranath Mahajan, Srinivas Pietambaram
  • Patent number: 12213242
    Abstract: According to the disclosure, an electronic device may include a printed circuit board, a first component disposed on one surface of the printed circuit board, a second component disposed on the other surface of the printed circuit board, and a metal structure configured to shield electromagnetic interference (EMI) related to the first component, wherein the metal structure includes a first portion configured to cover at least a part of the first component, and a second portion configured to extend from the first portion through the printed circuit board so as to support the second component. Various other embodiments may be possible.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: January 28, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungdae Son, Jongin Kim, Dongseon Lee
  • Patent number: 12205877
    Abstract: A method of manufacturing a component carrier includes forming a stack having electrically conductive layer structures and electrically insulating layer structures; configuring the stack as a redistribution structure for transferring between a smaller pitch on one side of the stack towards a larger pitch on an opposing side of the stack; and arranging a first layer structure and a second layer structure in opposing surface regions of the stack. The first layer structure includes a group of first electrically conductive elements arranged in a first density and the second layer structure includes a group of second electrically conductive elements arranged in a second density. At least one of the electrically conductive layer structures of the stack, which forms the redistribution structure, includes a group of vertically and/or horizontally arranged connections arranged in a third density. The third density is higher than the first density and higher than the second density.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: January 21, 2025
    Assignee: AT&S(Chongqing) Company Limited
    Inventor: Jeesoo Mok
  • Patent number: 12207395
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: January 21, 2025
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 12200862
    Abstract: Encapsulated electronic modules having complex contact structures may be formed by encapsulating panels containing a substrate comprising pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within terminal holes and other holes drilled in the panel within the boundaries of the cut lines. Slots may be cut in the panel along the cut lines. The interior of the holes, as well as surfaces within the slots and on the surfaces of the panel may be metallized, e.g. by a series of processes including plating. Terminals may be inserted into the terminal holes and connected to conductive features or plating within the holes. A conductive element may be provided on the substrate to connect to a terminal. Alternatively solder may be dispensed into the holes for surface mounting.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 14, 2025
    Assignee: Vicor Corporation
    Inventors: Patrizio Vinciarelli, Michael B. LaFleur
  • Patent number: 12200857
    Abstract: The present disclosure provides a package device including a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: January 14, 2025
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 12198581
    Abstract: A light emitting diode display device includes: a substrate, a plurality of signal lines, and a plurality of transparent apertures. A plurality of element packages arranged in matrix on one side of the substrate, the two element packages are connected by the signal lines, and the transparent aperture is surrounded by the signal lines. The signal line is a multi-layer structure for transmitting signal, which can reduce the risk of breaking the signal transmission line during stretching. The transparent aperture is stacked with organic materials, and the inorganic material is removed, which reduces the problem of the cracking and extension of the inorganic material layer when the product is stretched. It also has the effect of reducing the penetration loss caused by the refraction of light through multiple layers, so that the transparent aperture forms a high light-transmitting effect.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: January 14, 2025
    Assignee: General Interface Solution Limited
    Inventors: Po-Ching Lin, Po-Lun Chen, Chun-Ta Chen, Ya-Chu Hsu, Chia-Ming Fan
  • Patent number: 12200869
    Abstract: A dynamic flex circuit includes a plurality of hole sets arranged along the dynamic flexible circuit. The dynamic flex circuit also includes a plurality of actuator wires coupled to the dynamic flexible circuit by way of intertwining each of the plurality of actuator wires through each hole set in the plurality of hole sets arrange along the dynamic flexible circuit. Each of the plurality of actuator wires are configured to impart a motion onto the dynamic flexible circuit depending on the amount of heat applied to each of the plurality of actuator wires.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: January 14, 2025
    Assignee: THE AEROSPACE CORPORATION
    Inventors: Jerome K. Fuller, Todd Fillmore Sheerin
  • Patent number: 12193169
    Abstract: An improved electromagnetic field generating antenna is compatible with fluoroscopic imaging and can be placed under, above or anywhere around the patient. The antenna includes one or more antenna elements laid out on a single or multi-layer PCB with current conducting metal traces used for creating electromagnetic fields for tracking sensors. An antenna enclosure is made with a polymer or other non-conductive material. The antenna does not have to be moved for allowing medical imaging during various procedures. An X-ray filter may be made out of similar sub-components as a full antenna assembly with the sole purpose of reducing the radiation dose to the patient during medical procedures without negatively affecting the image quality.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: January 7, 2025
    Assignee: RadWave Technologies Inc.
    Inventors: Lev Koyrakh, Sean Morgan, Andrew Brown, Farhad Jafari, Ivy Lucia Forbes Miel, Michael R Weisenberger
  • Patent number: 12193154
    Abstract: The present disclosure provides a wiring structure, a display substrate and a display device, and belongs to the field of display technology. The wiring structure of the present disclosure comprises a body portion provided with hollow patterns; the body portion has a first side and a second side which are provided opposite to each other along an extending direction of the wiring structure, and both the first and second sides are wavy; the body portion comprises a plurality of conductive elements sequentially connected along the extending direction of the wiring structure; and in each conductive element, a length of a protruding portion on the first side in the extending direction of the wiring structure is different from that of a protruding portion on the second side in the extending direction of the wiring structure.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: January 7, 2025
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhifeng Zhan, Peng Huang, Yanxin Wang, Shuquan Yang, Wei Wang
  • Patent number: 12193167
    Abstract: A method of manufacturing an electronic device including the following steps is provided herein. A plurality of first electronic components is provided. The plurality of first electronic components is transferred onto a plurality of pickup sites. An empty pickup site from the plurality of pickup sites may be figured out, wherein the plurality of first electronic components is absent at the empty pickup site. A second electronic component is transferred onto the empty pickup site. A target substrate is provided. The plurality of first electronic components and the second electronic component are transferred onto the target substrate.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: January 7, 2025
    Assignee: Innolux Corporation
    Inventors: Kai Cheng, Fang-Ying Lin, Tsau-Hua Hsieh
  • Patent number: 12171060
    Abstract: A device for current determination includes a shunt and a device for temperature measurement including a printed circuit board, an evaluation unit and a temperature sensor. The printed circuit board has a milled groove which runs spirally around the temperature sensor, so that the temperature sensor is arranged on a printed circuit board plateau defined by the milled groove and is displaceable in a direction that is parallel to a normal vector of a plane defined by the printed circuit board.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: December 17, 2024
    Assignee: SMA Solar Technology AG
    Inventors: Felix Muehlhausen, Simon Butterweck
  • Patent number: 12167531
    Abstract: An electronic device includes a first housing having a first through-hole, of which a first opening and a second opening are communicated with each other, and a second housing connected to the first housing to be rotatable. A flexible printed circuit board (FPCB) extends from the first housing to the second housing via the first through-hole. The FPCB includes a plurality of layers, a first sealing member disposed in the first through-hole and surrounding the FPCB, and a lamination part toward the first sealing member. A portion of a first layer and/or a second layer corresponding to the second lamination part includes at least one first valley extending from a surface that faces an adjacent layer in a lengthwise direction of the FPCB. The lamination part includes a first adhesive layer interposed between the first layer and the second layer and filling the at least one first valley.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: December 10, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jihoon Kang, Jongmin Kang, Chungil Choi
  • Patent number: 12167544
    Abstract: A method for producing a wiring circuit board includes a first step of preparing a wiring circuit board assembly sheet including a support sheet, a plurality of wiring circuit boards supported by the support sheet, and a joint connecting the support sheet to the plurality of wiring circuit boards, having flat-shaped one surface and the other surface facing one surface at spaced intervals thereto in a thickness direction, and having a thin portion in which the other surface is recessed toward one surface and a second step of forming a burr portion protruding toward the other side in the thickness direction and cutting the thin portion.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 10, 2024
    Assignee: NITTO DENKO CORPORATION
    Inventors: Ryosuke Sasaoka, Naoki Shibata, Yasunari Oyabu