Abstract: Techniques for block storage using a hybrid memory device are described. In at least some embodiments, a hybrid memory device includes a volatile memory portion, such as dynamic random access memory (DRAM). The hybrid memory device further includes non-volatile memory portion, such as flash memory. In at least some embodiments, the hybrid memory device can be embodied as a non-volatile dual in-line memory module, or NVDIMM. Techniques discussed herein employ various functionalities to enable the hybrid memory device to be exposed to various entities as an available block storage device.

Abstract: Techniques for block storage using a hybrid memory device are described. In at least some embodiments, a hybrid memory device includes a volatile memory portion, such as dynamic random access memory (DRAM). The hybrid memory device further includes non-volatile memory portion, such as flash memory. In at least some embodiments, the hybrid memory device can be embodied as a non-volatile dual in-line memory module, or NVDIMM. Techniques discussed herein employ various functionalities to enable the hybrid memory device to be exposed to various entities as an available block storage device.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: generate mapping data defining mapping, from logical block addresses in namespaces configured on the non-volatile storage media, to logical block addresses in a capacity of the non-volatile storage media; maintain an active copy of the mapping data; generate cached copies of the mapping data from the active copy; generate a shadow copy from the active copy; implement changes in the shadow copy; after the changes are made in the shadow copy, activate the shadow copy and simultaneously deactivate the previously active copy; and update the cached copies according to the newly activated copy, as a response to the change in active copy identification.

Abstract: Embodiments of the invention include a machine-readable medium having stored thereon instructions, which if performed by a machine causes the machine to perform a method that includes assigning an urgency of requests based on a priority level for incoming requests and associated entries in at least one priority queue, assigning an urgency delta for anti-starvation that indicates urgency promotion to prevent starvation for the incoming requests in the at least one priority queue, determining conflict information including whether an incoming request is dependent on any request already present in the at least one queue, determining all contending requests within the at least one priority queue during a cycle, and sending a selected contending request to a memory controller for accessing memory.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller includes a host interface control circuit and a memory interface control circuit. When, within a period during which the controller is in a mode to manage mapping between logical addresses and physical addresses of the nonvolatile memory in units of management size corresponding to plural clusters, a skip write command with a skip mask indicating logical blocks to be transferred is received from a host, the host interface control circuit transfers write data to a buffer in units of clusters, and transmit plural write instructions to the memory interface control circuit when the cluster being currently transferred is the last valid cluster in the plural clusters.

Abstract: Techniques disclosed herein relate to a method performed on a computing device. The method includes receiving a request to execute an instruction specified to access a first unit of memory identified by a target address. The instruction is associated with a second unit of memory associated with a source address. The method also includes determining whether the request to execute the instruction is trusted to access the first memory unit based on the target address and the source address.

Abstract: A system and method are provided for pooling storage devices in a virtual library for performing a storage operation. A storage management device determines a storage characteristic of a plurality of storage devices with respect to performing a storage operation. Based on a storage characteristic relating to performing the storage operation, the storage management device associates at least two storage devices in a virtual library. The storage management device may continuously monitor the virtual library and detect a change in storage characteristics of the storage devices. When changes in storage characteristics are detected, the storage management device may change associations of the storage device in the virtual library.

Abstract: Provided are a computer program product, system, and method for pre-allocating storage space for an application operation in a space efficient volume. To transmit application requests to a storage controller managing a space efficient volume, a determination is made of an amount of space required for an application operation requiring a series of write operations over a period of time to the space efficient volume. A space pre-allocation request for the application operation is transmitted to the storage controller. The space pre-allocation request indicates a requested amount of physical space to pre-allocate to the application operation to cause the storage controller to pre-allocate the requested amount of space in advance of the application operation needing the requested amount of space in the volume for the series of write operations.

Abstract: Provided are a computer program product, system, and method for pre-allocating storage space for an application operation in a space efficient volume where a host system transmits writes to the space efficient volume. Physical storage space is allocated to the space efficient volume when the host system submits a write request. An amount of space needed by the write request is allocated to the volume in response to receiving the write request. A space allocation request is received from the host system for an application operation indicating a requested amount of space to allocate in the space efficient volume for the application operation. The requested amount of space is pre-allocated in the space efficient volume for the application operation in advance of the application operation needing the requested amount of space for a series of write operations that will be generated during the execution of the application operation.

Abstract: Techniques are described for providing processor-based dedicated fixed function hardware to perform runtime integrity measurements for detecting attacks on system supervisory software, such as a hypervisor or native Operating System (OS). The dedicated fixed function hardware is provided with memory addresses of the system supervisory software for monitoring. After obtaining the memory addresses and other information required to facilitate integrity monitoring, the dedicated fixed function hardware activates a lock-out to prevent reception of any additional information, such as information from a corrupted version of the system supervisory software. The dedicated fixed function hardware then automatically performs periodic integrity measurements of the system supervisory software. Upon detection of an integrity failure, the dedicated fixed function hardware uses out-of-band signaling to report that an integrity failure has occurred.

Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor is configured to perform the steps of: receiving a first head link for a page invalidation chain, the page invalidation chain including a plurality of page invalidation tables (PITs); receiving a second head link for an active real page table (RPT) chain, the active RPT chain including a plurality of RPTs; accessing a PIT, wherein the PIT includes a first data structure and a second data structure; invalidating the one or more RPTs, whereas the one or more RPTs are invalidated simultaneously in a batch; and releasing the one or more RPTs to a free RPT chain, the free RPT chain includes a plurality of released RPTs.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: System and method for transferring data between a host system and a data storage system is provided. The system includes an interface that uses a file based protocol to transfer data between the data storage system and the host system, wherein the data storage system includes a first mass storage device and a second mass storage device; wherein the first mass storage device is a solid state non-volatile memory device and the second mass storage device is a non-solid state memory device. The first mass storage device is a flash memory device that operates as a primary storage device that stores data on a file by file basis. The second mass storage device is a magnetic disk drive that operates as secondary storage device and stores data received via a logical interface.

Abstract: A data storage system and associated method are provided wherein a policy engine continuously collects qualitative information about a network load to the data storage system in order to dynamically characterize the load and continuously correlates the load characterization to the content of a command queue of transfer requests for writeback commands and host read commands, selectively limiting the content with respect to writeback commands to only those transfer requests for writeback data that are selected on a physical zone basis of a plurality of predefined physical zones of a storage media.

Abstract: System and method for transferring data between a host system and a data storage system is provided. The system includes an interface that uses a file based protocol to transfer data between the data storage system and the host system, wherein the data storage system includes a first mass storage device and a second mass storage device; wherein the first mass storage device is a solid state non-volatile memory device and the second mass storage device is a non-solid state memory device. The first mass storage device is a flash memory device that operates as a primary storage device that stores data on a file by file basis. The second mass storage device is a magnetic disk drive that operates as secondary storage device and stores data received via a logical interface.

Abstract: Providing flexible management of heterogeneous memory systems using spatial Quality of Service (QoS) tagging in processor-based systems is disclosed. In one aspect, a heterogeneous memory system of a processor-based system includes a first memory and a second memory. The heterogeneous memory system is divided into a plurality of memory regions, each associated with a QoS identifier (QoSID), which may be set and updated by software. A memory controller of the heterogeneous memory system provides a QoS policy table, which operates to associate each QoSID with a QoS policy state, and which also may be software-configurable. Upon receiving a memory access request including a memory address of a memory region, the memory controller identifies a software-configurable QoSID associated with the memory address, and associates the QoSID with a QoS policy state using the QoS policy table. The memory controller then applies the QoS policy state to perform the memory access operation.

Abstract: A write request is received to write a data block having a logical block address to a nonvolatile storage device. The method includes writing a value of the data block to the nonvolatile storage device. The writing includes locating a position in a tree-based data structure that includes first and second nodes. The first node is configured to store a first set of data blocks having logical block addresses in a first numerical range, and the second node is configured to store a second set of data blocks having logical block addresses in a second numerical range. The position is located in the first node or the second node depending on the value of the logical block address. The writing includes storing the value of the data block in the position in the tree-based data structure.

Abstract: A method is disclosed for only permitting data from a host to be written to a first non-volatile memory layer and only permitting data to be written into a second non-volatile memory layer via a maintenance operation over a single data path between the layers. The single data path may be an on-chip copy data path. A memory system includes a multi-layer non-volatile memory and data management circuitry, where the data management circuitry includes data flow path circuitry defining only a single data path for programming any data into the second layer. Maintenance manager circuitry and programming interleave circuitry in the data management circuitry are configured to select a maintenance schedule, and to interleave programming of host data with maintenance operation writes for the selected maintenance schedule only along the one or more data paths defined by the data flow path circuitry.

Abstract: A database system may include a memory device that includes a least a portion to serve as a buffer cache and an array of persistent storage devices configured to store data of a database. The database system may monitor a frequency of data value associated with a first portion of data of the database stored in the buffer cache. The database system may maintain the first portion of data in the buffer cache in response to the frequency of data value associated with the first portion of data being greater than a frequency of data value associated with at least a portion of the data of the database stored in the array of persistent storage devices.

Abstract: A memory module includes: a first memory device that is volatile or non-volatile; a second memory device that is non-volatile; a third memory device that is non-volatile; and a controller that controls the first to third memory devices, wherein a capacity of the second memory device is larger than a capacity of the first memory device, and a capacity of the third memory device is larger than the capacity of the second memory device, a second upper limit value of the number of rewritings of the second memory device is larger than a third upper limit value of the number of rewritings of the third memory device, and a first upper limit value of the number of rewritings of the first memory device is larger than the second upper limit value of the number of rewritings of the second memory device, and the controller accesses the second memory device with reference to a first address translation table related to the second memory device stored in the first memory device, and accesses the third memory device with ref