Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space. Instructions that modify the main address space are intercepted, storage delta packets are generated based on intercepted instructions, and the storage delta packets are sent to a service co-processor maintaining a service address space.

Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor where the main processor is provided with a main address space. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor updates the service address space with storage delta packets received from the main processor, and the service co-processor performs diagnostic services based on command packets received from the main processor.

Abstract: A method for data storage includes storing data in a set of memory blocks of a non-volatile memory. Each memory block, which holds a respective portion of the data, is classified as valid or invalid depending on whether the memory block holds a most updated version of the portion, and as anchor or non-anchor depending on whether the portion belongs to a coherent snapshot of the data. Upon recovering from a power interruption, the coherent snapshot of the data is reconstructed from the memory blocks, based on classification of the memory blocks as valid or invalid and as anchor or non-anchor.

Abstract: A storage layer is configured to store data at respective offsets within storage units of a storage device. Physical addresses of the data may be segmented into a first portion identifying the storage unit in which the data is stored, and a second portion that indicates the offset of the data within the identified storage unit. An index of the data offsets (e.g., second portions of the physical addresses) may be persisted on the storage device. The first portion of the address may be associated with logical addresses of the data in a forward index. The forward index may omit the second portion of the physical addresses, which may reduce the memory overhead of the index and/or allow the forward index to reference larger storage devices. Data of a particular logical address may be accessed using the first portion of the physical address maintained in the forward index, and the second portion of the media address stored on the storage device.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A system for storing data includes a performance storage unit, a performance storage transfer manager, a segment storage system, and a performance segment storage unit. The performance storage unit is for storing a data stream or a data block in. The data stream or the data block includes one or more data items. The performance storage transfer manager manages a transfer of the one or more data items to be automatically stored in the segment storage system over a network. The segment storage system is for storing a stored data item of the one or more data items as a set of segments. The performance segment storage unit is for storing the set of segments in the event that the stored data item has been stored using the segment storage system.

Abstract: System and methods are provided for storing address-mapping data from a storage device on a processing system. Address-mapping data is stored on a non-volatile memory of a storage device, the address-mapping data indicating mapping from logical addresses to physical addresses of the non-volatile memory of the storage device. The address-mapping data is transmitted from the non-volatile memory to a processing system. In response to a request to access a logical address of the non-volatile memory, part of the address-mapping data is transferred from the processing system to a volatile memory of the storage device, the part of the address-mapping data being associated with a mapping from the logical address to a physical address of the non-volatile memory.

Abstract: A method for migrating a virtual machine disk (VM disk) from first physical storage to second physical storage while the virtual machine (VM) is running, the method comprising: (a) creating a first child VM disk to which writes are redirected from a first parent VM disk, the first parent VM disk being on the first physical storage; (b) copying the first parent VM disk to the second physical storage as a second parent VM disk; (c) re-parenting the first VM child disk to the second parent VM disk; and (d) consolidating the first child VM disk and the second parent VM disk.

Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. The memory card also includes a memory module, a hub device and pins for boundary scan signals.

Abstract: A method and apparatus for implementing a storage optimization process is provided. The method includes identifying a file for storage on a storage device. The storage device determines that the file comprises a file size that exceeds multiple physical disk blocks of the storage device by a fractional value. The file is divided into a first portion and a second portion. The first portion comprises a file size such that the first portion fits entirely within a first single block of the storage device. The second portion comprises a size such that the second portion exceeds a size of a second single block of the storage device by the fractional value. The first portion is stored within the first single block. The second portion is compressed such that a resulting compressed file fits entirely within the second single block.

Abstract: Methods, systems, and computer readable media for automatically deriving hints from storage device accesses and from file system metadata and for utilizing the hints to optimize utilization of the memory storage device are provided. One method includes analyzing an input/output operation involving non-volatile memory or file system metadata. The method further includes automatically deriving, based on results from the analyzing, a hint regarding an expected access pattern to the non-volatile memory. The method further includes using the hint to optimize utilization of the non-volatile memory.

Abstract: Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.

Abstract: A system, a method and a computer program product for managing memory access of an avionics control system having at least one control computer having at least one memory control device. The method includes assigning a memory access of at least one unique memory region of at least one memory unit to each of at least one application task or task set. A memory access of at least one application data update task is assigned to at least one subregion of one or more of the at least one unique memory region. At least one data parameter is written to the at least one subregion and the assigned memory access of the at least one application data update task de-activated.

Abstract: An apparatus including a processor caused to: receive sizes and data block encryption data for multiple encrypted data blocks from multiple node devices, wherein data block encryption data is separately generated and used by each node device to encrypt a portion of a data set to generate one of the multiple encrypted data blocks; for each encrypted data block, generate a corresponding map entry within map data to include size and data block encryption data; and in response to receiving size and data block encryption data for all encrypted data blocks, encrypt a portion of the map data to generate an encrypted map base, wherein the portion of map data includes at least a subset of the multiple map entries, and transmit the encrypted map base to one or more storage devices to be stored within a data file along with the multiple encrypted data blocks.

Abstract: The invention provides a flash memory which may effectively protect information with a high security level. A flash memory includes a setting part. When the setting part is inputted a specific command, the setting part sets up specific address information to a nonvolatile configuration register, and sets up specific data in a hidden storage region. The flash memory also includes: a comparing part, which compares inputted address information and the specific address information during a reading operation; and a control part, which reads specific data set in the storage region and erases a specific address when two address information are consistent, and reads data stored in a memory array according to the inputted address information when two address information are inconsistent.

Abstract: Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for model based configuration parameter management. An association module is configured to group a plurality of erase blocks of a non-volatile memory medium based on an amount of time since data has been written to the plurality of erase blocks. A read module is configured to sample data of at least two word lines from at least one erase block from each of a plurality of groups of erase blocks. A configuration parameter module is configured to determine different read voltage thresholds for different word lines of groups of erase blocks using different read voltage threshold models for different groups based on sampled data.

Abstract: In an approach for writing data on a tape using a file system, a processor receives a first write request of a first file. A processor obtains data of the first file. A processor writes the data of the first file on a tape. A processor receives a second write request of a second file prior to completion of writing the data of the first file on the tape. A processor adds information about the second file to a first list, wherein the first list includes files waiting to write. Subsequent to writing the data of the first file on the tape, a processor obtains data of the second file based on the first list. A processor writes the data of the second file after the first file on the tape.

Abstract: Described are techniques for memory management. An N-level bitmap is received, N>2. A memory pool is partitioned into slots each slot having a corresponding bit in level-1 of the N-level bitmap that indicates whether the slot is used or free. The slots are grouped into a hierarchy including N levels. A first thread receives a first request to allocate a first slot of the memory pool. Responsive to receiving the first request, the first thread performs first processing to allocate the first slot using the N-level bitmap. Allocation requests each to allocate slots from the memory pool are only processed by the first thread. A second thread receives a second request to free a second slot of the memory pool. Responsive to receiving the second request, the second thread performs second processing using the N-level bitmap to free the second slot. Requests to free slots are processed by multiple threads.

Abstract: In a multithreaded data processing system including a plurality of processor cores and a system fabric, translation entries can be invalidated without deadlock. A processing unit forwards translation invalidation request(s) received on the system fabric to a processor core via a non-blocking channel. Each of the translation invalidation requests specifies a respective target address and requests invalidation of any translation entry in the processor core that translates its respective target address. Responsive to a translation snoop machine of the processing unit snooping broadcast of a synchronization request on the system fabric of the data processing system, the translation synchronization request is presented to the processor core, and the translation snoop machine remains in an active state until a signal confirming completion of processing of the one or more translation invalidation requests and the synchronization request at the processor core is received and thereafter returns to an inactive state.