Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

Abstract: A semiconductor system comprises a nonvolatile memory storing a patch code, the patch code comprising a unique identifier (ID). An internal read only memory (IROM) stores a boot code, the boot code comprising a patch code execution function for executing the patch code and a linked register (LR) address for specifying a storage location where the patch code is to be executed. A static random access memory (SRAM) stores a copy of the patch code at the storage location, the copy of the patch code including the unique ID. A processor executes the copy of the patch code from the storage location. The processor executes the copy of the patch code stored at the storage location in the SRAM according to the comparison result.

Abstract: A system and method can provide a scalable data storage in a middleware environment. The system can include a cluster of replicated store daemon processes in a plurality of processing nodes, wherein each machine node can host a replicated store daemon process of the cluster of replicated store daemon processes. Additionally, the system can include one or more replicated stores associated with an application server the processing node. The replicated store daemon cluster can persist data from a replicated store to another node, the other node also being associated with the replicated store daemon cluster. The system and method can additionally support a messaging service in a middleware environment. The messaging service can use the replicated store to store a copy of a message in the local processing node and on another processing node associated with the same replicated store daemon cluster.

Abstract: Example embodiments of the present invention relate to a method, an apparatus, and a computer program product for mirroring data in a data storage system across a first storage device having a first latency and a second storage device having a second latency. The method includes receiving an I/O at the data storage system and controlling the I/O to the first storage device having the first latency or the second storage device having the second latency according to properties of the I/O and properties of the first storage device having the first latency and the second storage device having the second latency.

Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.

Abstract: A technique for handling storage commands includes receiving, by an interface node of a data storage system, a first storage command. The interface node determines whether the first storage command is a head of queue (HOQ) command. In response to determining the first storage command is an HOQ command, the interface node increments a constrained command count and issues the first storage command to a first worker processor core for processing. In response to determining the first storage command is not an HOQ command, the interface node processes the first storage command as a non-HOQ command.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for configuring memory in an effort to reduce power consumption. For example, certain aspects of the present disclosure may provide an apparatus having a processing system configured to determine an operating mode of an application executing on the processing system. The operating mode may be one of a plurality of operating modes of the application, and each operating mode of the plurality of operating modes may correspond to a different configuration of memory. In certain aspects, the configurations of memory may correspond to different portions of memory that are active or inactive. In certain aspects, the apparatus may also include a memory control module configured to configure the memory based on the determined operating mode of the application.

Abstract: The disclosure relates to technology for predicting file access patterns by identifying one or more files stored in a first cache and one or more pages associated with each of the one or more files in a second cache. The one or more files in the first cache are evicted based on a first eviction policy and, for each of the one or more files, the one or more pages in the second cache are evicted based on a second eviction policy. Access patterns of the one or more files based on the first and second eviction policies may then be predicted.

Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.

Abstract: Techniques related to cache management for multi-node databases are disclosed. In some embodiments, a system comprises one or more computing devices including a training component, data store, cache, filtering component, and listening component. The training component produces a plurality of models based on user interaction data. The plurality of models are stored in the data store, which responds to requests from the cache when the cache experiences cache misses. The cache stores a first subset of the plurality of models. The filtering component selects a second subset of the plurality of models based on one or more criteria. Furthermore, the filtering component sends the second subset of the plurality of models to a messaging service. The listening component retrieves the second subset of the plurality of models from the messaging service. Furthermore, the listening component causes the second subset of the plurality of models to be stored in the cache.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.

Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Abstract: A solid state memory system includes: an interface circuit; a device processor, coupled to the interface circuit, configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command; a non-volatile memory array coupled to the interface circuit; and a power manager unit, coupled between the device processor and the non-volatile memory array, configured to alter an operating configuration of the non-volatile memory array to meet the requirement of the dynamic power limit command.

Abstract: Techniques for block storage using a hybrid memory device are described. In at least some embodiments, a hybrid memory device includes a volatile memory portion, such as dynamic random access memory (DRAM). The hybrid memory device further includes non-volatile memory portion, such as flash memory. In at least some embodiments, the hybrid memory device can be embodied as a non-volatile dual in-line memory module, or NVDIMM. Techniques discussed herein employ various functionalities to enable the hybrid memory device to be exposed to various entities as an available block storage device.

Abstract: Techniques for block storage using a hybrid memory device are described. In at least some embodiments, a hybrid memory device includes a volatile memory portion, such as dynamic random access memory (DRAM). The hybrid memory device further includes non-volatile memory portion, such as flash memory. In at least some embodiments, the hybrid memory device can be embodied as a non-volatile dual in-line memory module, or NVDIMM. Techniques discussed herein employ various functionalities to enable the hybrid memory device to be exposed to various entities as an available block storage device.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: generate mapping data defining mapping, from logical block addresses in namespaces configured on the non-volatile storage media, to logical block addresses in a capacity of the non-volatile storage media; maintain an active copy of the mapping data; generate cached copies of the mapping data from the active copy; generate a shadow copy from the active copy; implement changes in the shadow copy; after the changes are made in the shadow copy, activate the shadow copy and simultaneously deactivate the previously active copy; and update the cached copies according to the newly activated copy, as a response to the change in active copy identification.

Abstract: Embodiments of the invention include a machine-readable medium having stored thereon instructions, which if performed by a machine causes the machine to perform a method that includes assigning an urgency of requests based on a priority level for incoming requests and associated entries in at least one priority queue, assigning an urgency delta for anti-starvation that indicates urgency promotion to prevent starvation for the incoming requests in the at least one priority queue, determining conflict information including whether an incoming request is dependent on any request already present in the at least one queue, determining all contending requests within the at least one priority queue during a cycle, and sending a selected contending request to a memory controller for accessing memory.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller includes a host interface control circuit and a memory interface control circuit. When, within a period during which the controller is in a mode to manage mapping between logical addresses and physical addresses of the nonvolatile memory in units of management size corresponding to plural clusters, a skip write command with a skip mask indicating logical blocks to be transferred is received from a host, the host interface control circuit transfers write data to a buffer in units of clusters, and transmit plural write instructions to the memory interface control circuit when the cluster being currently transferred is the last valid cluster in the plural clusters.

Abstract: Techniques disclosed herein relate to a method performed on a computing device. The method includes receiving a request to execute an instruction specified to access a first unit of memory identified by a target address. The instruction is associated with a second unit of memory associated with a source address. The method also includes determining whether the request to execute the instruction is trusted to access the first memory unit based on the target address and the source address.