Abstract: Techniques perform resource reallocation for a disk system. Such techniques involve: determining, based on conditions of allocated disk extents in a plurality of disks and wear levels of the plurality of disks, an enhanced neighbor matrix characterizing both distribution evenness of the disk extents on the plurality of disks and the wear levels of the plurality of disks; and performing a resource reallocation operation on the plurality of disks based on the enhanced neighbor matrix. Accordingly, it is possible to, through the enhanced neighbor matrix that is based on the wear level, simultaneously consider both the distribution evenness of disk extents and the wear level of the disk while performing resource reallocation, thereby avoiding the problem of ping-pang resource reallocation caused by inconsistent standards between different resource reallocation methods, and having good compatibility with existing storage systems.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

Abstract: A memory system includes a memory controller, a first memory, and a second memory. The memory controller has a command address port, a chip select port, a first data port, and a second data port. The first memory is coupled to the command address port, the chip select port, and the first data port, and the second memory is coupled to the command address port, the chip select port, and the second data port. The capacity of the second memory is greater than the capacity of the first memory. The memory controller controls the first memory and the second memory simultaneously through the command address port and the chip select port.

Abstract: A data storage device may include a storage; and a controller, wherein the controller comprises: an address translator configured to generate multiple map data, each including a physical address of the storage corresponding to a logical address and multiple meta data for the multiple map data respectively; a descriptor cache manager configured to add new meta data to a storage area of a descriptor cache, the storage area for the new meta data being physically continuous with a storage area in which last meta data, of the multiple meta data, is stored and assign a head pointer and a tail pointer to select positions in the descriptor cache; a map cache manager configured to store the multiple map data in a map cache; and a map search component configured to search the descriptor cache according to a search range determined by the head pointer and the tail pointer.

Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Abstract: The present disclosure generally relates to methods of operating storage devices. A controller of the storage device is configured to retrieve a first command to write data to one or more first logical blocks of a first zone, and direct memory access (DMA) read and write the data associated with the first command to the first logical blocks. The first logical blocks are between a zone starting point of the first zone and a zone capacity of the first zone. The controller is configured to retrieve a second command to write data to one or more second logical blocks of the first zone, and DMA read and write the data associated with the second command to the second logical blocks. The second logical blocks are between the zone starting and the zone capacity of the first zone, and the first logical blocks are non-sequential to the second logical blocks.

Abstract: Embodiments disclosed herein provide systems, methods, and computer readable media for sub-cluster recovery in a data storage environment having a plurality of storage nodes. In a particular embodiment, the method provides scanning data items in the plurality of nodes. While scanning, the method further provides indexing the data items into an index of a plurality of partition groups. Each partition group includes data items owned by a particular one of the plurality of storage nodes. The method then provides storing the index.

Abstract: A host unit of an information processing apparatus has a command issuing block for issuing access requests to a flash memory, the issued commands being dividedly stored in two or more queues according to the contents and emergency level of access. A management command generating block of a flash controller generates requests for the processing necessary for the management of the flash memory, the requests being stored in any one of the queues. Following the rules set for each queue, a command processing block reads commands by switching between the queues and processes the commands.

Abstract: A memory system may include: a nonvolatile memory device including a plurality of memory blocks, each memory block including a plurality of pages; and a controller suitable for controlling the nonvolatile memory device to store user data received from a host in a first block among the memory blocks, to store metadata in a second block among the memory blocks, and to generate the metadata corresponding to storage of the user data, the controller may map a first logical address used in the host to a physical address of the first block, and may map a second logical address not used in the host, to a physical address of the second block, the first logical address and the second logical address being successive.

Abstract: A data storage device may include a nonvolatile memory apparatus and a controller. The controller may be configured to translate a logical address into a physical address when receiving a host command (such as a write command or a read command) including the logical address from a host device, to generate a pre-command including the physical address, to transmit the generated pre-command to the nonvolatile memory apparatus before completing one or more remaining operations of the operations used to process the host command, and to transmit a confirm command to the nonvolatile memory apparatus when the remaining operations are complete. The controller may perform the remaining operations and the transmission of the pre-command to the nonvolatile memory apparatus at the same time.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the named portion to the logical addresses defined for the entire non-volatile storage media.

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

Abstract: A memory controller for processing a flush request includes: a request message controller configured to generate a command or control signal in response to a request of a host, a delay time determiner configured to, when the request is a current flush request, generate delay information based on a number of write requests between a last received flush request before the current flush request and the received flush request and a response message controller configured to generate a flush response corresponding to the received flush request message based on the delay information.

Abstract: A method of managing operation of a data storage system (DSS) is provided. The method includes (a) reserving space within a dedicated metadata storage region (DMSR); (b) in response to determining that accommodating a storage request requires use of the reserved space, entering a restricted write mode; (c) while operating in the restricted write mode, using the reserved space in a process that frees space within the DMSR outside the reserved space; and (d) exiting the restricted mode in response to freeing space within the DMSR outside the reserved space. An apparatus, system, and computer program product for performing a similar method are also provided.

Abstract: A solid state memory system includes: an interface circuit; a device processor configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command; a non-volatile memory array coupled to the interface circuit; and a power manager unit, coupled to the device processor, configured by the device processor, the power manager unit configured to adjust voltages for read, write, erase, and monitoring a voltage feedback in order to verify the dynamic power limit command is not exceeded; and a data error detection-and-correction unit, coupled to the power manager unit, configured to pause correction of error data, select a low power error correction code unit, enable a reduced ECC array, switch from error detection-and-correction to error detection, or a combination thereof in response to the dynamic power limit command.

Abstract: A system includes a volatile memory having buffers and a processing device. A command generation processor receives, from a host, a read request with a logical block address (LBA) and creates a first logical transfer unit (LTU), including the first LBA, that is to be mapped to a physical address. The command generation processor reads a flag to determine that the first LTU is associated with a zone of LBA address space, the zone including sequential LBAs that are sequentially mapped to sequential physical addresses. The command generation processor generates command tags that are to direct the processing device to retrieve the data from the memory device and store the data in a set of the buffers, where the command tags include a first command tag associated with the physical address and a second command tag associated with a second physical address that sequentially follows the physical address.

Abstract: Described herein is a memory architecture that is configured to dynamically determine an address encoding to use to encode multi-dimensional data such as multi-coordinate data in a manner that provides a coordinate bias corresponding to a current memory access pattern. The address encoding may be dynamically generated in response to receiving a memory access request or may be selected from a set of preconfigured address encodings. The dynamically generated or selected address encoding may apply an interleaving technique to bit representations of coordinate values to obtain an encoded memory address. The interleaving technique may interleave a greater number of bits from the bit representation corresponding to the coordinate direction in which a coordinate bias is desired than from bit representations corresponding to other coordinate directions.

Abstract: Compression of data for a file system utilizing protection groups can be implemented and managed. A compression management component (CMC) can control compression of data via inline or post-process compression for storage in protection groups in memory, including determining whether to compress data, determining a compression algorithm to utilize to compress data, and/or determining whether to perform inline and/or post-process compression of data. CMC can generate protection group (PG) metadata for a PG in which compressed data is stored. PG metadata can comprise a logical extent map that describes which logical blocks contain compressed data, a list of cyclic redundancy check values for logical blocks, and a list of compression chunks that store individual metadata regarding individual compressed streams, wherein, for an individual compressed stream, the individual metadata comprises a compression format, compressed size, uncompressed size, and/or starting offset in physical space within the PG.

Abstract: Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.

Abstract: A memory system includes a memory medium including a plurality of matrices and a plurality of data input/output (I/O) terminals, a row address adding circuit configured to add row address additive values to an input row address for accessing memory cells of the plurality of matrices, and a column address adding circuit configured to add column address additive values to an input column address for accessing to memory cells of the plurality of matrices. The plurality of matrices are configured into a plurality of matrix sub-groups, wherein each matrix sub-group includes matrices accessed through the same data I/O terminal. The row address additive values are different from each other according to the matrix sub-groups, and the column address additive values are different from each other according to the matrix sub-groups.