Abstract: Compression of data for a file system utilizing protection groups can be implemented and managed. A compression management component (CMC) can control compression of data via inline or post-process compression for storage in protection groups in memory, including determining whether to compress data, determining a compression algorithm to utilize to compress data, and/or determining whether to perform inline and/or post-process compression of data. CMC can generate protection group (PG) metadata for a PG in which compressed data is stored. PG metadata can comprise a logical extent map that describes which logical blocks contain compressed data, a list of cyclic redundancy check values for logical blocks, and a list of compression chunks that store individual metadata regarding individual compressed streams, wherein, for an individual compressed stream, the individual metadata comprises a compression format, compressed size, uncompressed size, and/or starting offset in physical space within the PG.

Abstract: Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.

Abstract: A memory system includes a memory medium including a plurality of matrices and a plurality of data input/output (I/O) terminals, a row address adding circuit configured to add row address additive values to an input row address for accessing memory cells of the plurality of matrices, and a column address adding circuit configured to add column address additive values to an input column address for accessing to memory cells of the plurality of matrices. The plurality of matrices are configured into a plurality of matrix sub-groups, wherein each matrix sub-group includes matrices accessed through the same data I/O terminal. The row address additive values are different from each other according to the matrix sub-groups, and the column address additive values are different from each other according to the matrix sub-groups.

Abstract: Described are techniques for dynamic rebalancing in storage systems. The techniques including a method comprising calculating an estimated time to storage fullness for respective storage pools in a space balance group, the estimated time to storage fullness based on an allocation speed of the respective storage pools. The method further comprises classifying a first storage pool having a first estimated time to storage fullness below a migration time threshold as a first migration source storage pool. The method further comprises classifying a second storage pool having a second estimated time to storage fullness above the migration time threshold as a first migration target storage pool. The method further comprises rebalancing free space in the space balance group by migrating storage volumes from the first migration source storage pool to the first migration target storage pool.

Abstract: Disclosed are various embodiments for loading a network site that uses a hierarchical site model. A computing device receives a request to generate a user interface associated with a network site. A caching process is initiated that caches data associated with the network site. A hierarchical site model is retrieved and processed to identify a subset of page models of the network site for generation of the user interface. Once it is determined that one of the subset of page models is stored in the cache, it is retrieved from the cache for generation of the user interface.

Abstract: Methods and systems for backing up and restoring different point in time versions of a virtual machine, a real machine, an application, a database, or a set of electronic files using a plurality of independently managed snapshot chains are described. The different point in time versions of the data being backed-up may be stored using two or more snapshot chains corresponding with two or more data partitions of the data being backed-up. Over time, additional full image snapshots may be acquired from an external server or generated locally by a storage appliance to limit the snapshot chain lengths and to limit the aggregate block chain lengths for the snapshot chains. Acquisition and generation of the additional full image snapshots may be staggered across different data partitions to limit computational and storage costs per snapshot.

Abstract: A storage system switching mediators within a storage system synchronously replicating data, where the switching between mediators includes: determining, among one or more of the plurality of storage systems, a change in availability of a first mediator service, wherein one or more of the plurality of storage systems are configured to request mediation from the first mediator service; communicating, among the plurality of storage systems and responsive to determining the change in availability of the first mediator service, a second mediator service to use in response to a fault; and switching, in dependence upon the change in availability of the first mediator service, from the first mediator service to the second mediator service.

Abstract: To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.

Abstract: A memory system includes a plurality of memory devices configuring a plurality of ways, and a memory controller communicating with the plurality of memory devices through a channel, wherein each of the plurality of memory devices includes a device queue, and wherein the device queue queues a plurality of controller commands inputted from the memory controller.

Abstract: An integrated circuit device includes a nonvolatile memory, first and second buffer memories, and a controller. Each of the first and second buffer memories is configured to buffer write data to be written to the nonvolatile memory in response to a write request and also buffer read data received from the nonvolatile memory in response to a read request. A controller is provided, which evaluates the first buffer memory against at least one criterion relating to data accuracy. The controller is configured to: redirect at least some of the write data from the first buffer memory to the second buffer memory in response to the write request when the evaluation demonstrates the criterion has been exceeded, and redirect at least some of the read data from the first buffer memory to the second buffer memory in response to the read request when the evaluation demonstrates the criterion has been exceeded.

Abstract: A memory access system includes a memory that is abstracted into data structures. The memory access system further includes a processor that generates an access request for accessing the abstracted memory by way of a structure access circuit of the memory access system. As the memory is abstracted into the data structures and the processor accesses the abstracted memory using the data structures, an addressing capability of the processor is extended. Further, the computing overhead of the processor is reduced, as the processor performs various memory operations by accessing the memory by way of the structure access circuit.

Abstract: Circuitry comprises memory circuitry providing a plurality of memory locations; location selection circuitry to select a set of one or more of the memory locations by which to access a data item according to a mapping relationship between an attribute of the data item and the set of one or more memory locations; the location selection circuitry being configured to initiate an allocation operation for a data item when that data item is to be newly stored by the memory circuitry and the selected set of one or more of the memory locations are already occupied by one or more other data items, the allocation operation comprising an operation to replace at least a subset of the one or more other data items from the set of one or more memory locations by the newly stored data item; and detector circuitry to detect a data access conflict in which a group of two or more data items having different respective attributes are mapped by the mapping relationship to the same set of one or more memory locations; the locat

Abstract: Embodiments of the present disclosure relate to a method an apparatus and a computer program product for constructing a scalable storage device by constructing the scalable storage device by combining a plurality of modularized building blocks; wherein each modularized building block in the plurality of modularized building blocks comprises a magnetic disk enclosure; and at least one modularized building block in the plurality of modularized building blocks comprises a storage processor, the storage processor comprising an input output processing unit; forming a cluster using the input output processing unit in the at least one modularized building block; and processing, using the cluster, an input or output (I/O) request from a host and metadata service.

Abstract: Disclosed is a technique in which an application can record changes it makes to physical memory. In the technique, the application specifies a virtual memory region which is converted to a plurality of cache lines, each of which is monitored for changes by a device connected to a coherence interconnect coupled to the processor caches. The application sends a start signal to start the logging process and an end signal to stop the process. During the logging process, when a change occurs to one of the cache lines, an undo entry corresponding to the change is created and entered into a transaction log residing in persistent memory. The transaction log containing the undo entries makes the set of changes recorded in the transaction log atomic. If a failure occurs, the recorded changes can be undone as if they never occurred.

Abstract: One embodiment facilitates a storage system, which comprises a backplane and a plurality of storage medium cards coupled to the backplane. The backplane is coupled to a host via a first interface, and the backplane comprises global management circuitry coupled to a plurality of groups of components and configured to process an input/output (I/O) request and manage a mapping table. A respective group of components includes: first circuitry configured to perform first computing operations; and second circuitry configured to perform second computing operations. A respective storage medium card is allowed to operate without a controller residing on the storage medium card. Data associated with the I/O request is processed by the global management circuitry and further processed by first circuitry and second circuitry associated with a storage medium card selected for executing the I/O request.

Abstract: Provided is a method for performing a background operation in a data processing system, including: selecting a sacrificial memory block from a plurality of memory blocks provided in a memory device; and transferring current valid data stored in the selected sacrificial memory block to a first memory in a host when an available capacity of the first memory is larger than or equal to a size of the current valid data.

Abstract: Techniques for block storage using a hybrid memory device are described. In at least some embodiments, a hybrid memory device includes a volatile memory portion, such as dynamic random access memory (DRAM). The hybrid memory device further includes non-volatile memory portion, such as flash memory. In at least some embodiments, the hybrid memory device can be embodied as a non-volatile dual in-line memory module, or NVDIMM. Techniques discussed herein employ various functionalities to enable the hybrid memory device to be exposed to various entities as an available block storage device.

Abstract: Techniques are disclosed that allow for retroactively capturing a debug/trace-level log without experiencing the severe performance degradation that obtaining such a log would otherwise entail. Trace-level logging is performed by maintaining a buffer of log messages for application events. The buffer is allocated a memory having very fast write speeds, and writing such messages into the buffer has a negligible performance impact. Many of the messages written into the buffer may not be important or useful at the time they are written. However, when a failure occurs, the messages may be useful for figuring out what when wrong. Responsive to detecting a failure or other anomalous event, the buffer of messages is automatically written to a permanent storage. Although writing to the permanent storage may be slow, the performance degradation is only incurred when a failure occurs.

Abstract: Provided is a method of storing data in a distributed environment including a plurality of storage devices, the method including: receiving a request to store the data; calculating a hash value by applying a hashing function to a value associated with the data; splitting the hash value into a plurality of weights, each weight corresponding to one of a plurality of chunks; selecting a chunk of the plurality of chunks based on the weight; and storing the data in a corresponding storage device, the corresponding storage device corresponding to the selected chunk.

Abstract: The present disclosure is directed to a memory management method and to a memory management device arranged to execute memory allocation and/or memory deallocation by use of segregated free lists, which provide information on memory chunks, wherein the memory allocation and/or the memory deallocation are executed according to states of the memory chunks, and wherein the states of the memory chunks comprise: an used state indicating that a memory chunk, which is in used state, is in use, and is not available for allocation; a linked state indicating that a memory chunk, which is in linked state, is not used, is linked within a free list of the segregated free lists, and is available for allocation; a free state indicating that a memory chunk, which is in free state, is not used, is not linked within any of the segregated free lists, and is not available for allocation.