Patents Examined by Yosef Gebreyesus
  • Patent number: 10714414
    Abstract: A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10714599
    Abstract: A semiconductor device including a first fin type pattern and a second fin type pattern which protrude from a substrate and are spaced apart from each other to extend in a first direction, a dummy fin type pattern protruding from the substrate between the first fin type pattern and the second fin type pattern, a first gate structure extending in a second direction intersecting with the first direction, on the first fin type pattern, a second gate structure extending in the second direction, on the second fin type pattern, and a capping pattern extending in the second direction, on the first gate structure and the second gate structure, wherein the capping pattern includes a separation part which is in contact with an upper surface of the dummy fin type pattern, and the dummy fin type pattern and the separation part separate the first gate structure and the second gate structure.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun II Lee, Sung II Park, Jae Hyun Park, Hyung Suk Lee
  • Patent number: 10707118
    Abstract: Systems and methods herein are related to the formation of optical devices including stacked optical element layers using silicon wafers, glass, or devices as substrates. The optical elements discussed herein can be fabricated on temporary or permanent substrates. In some examples, the optical devices are fabricated to include transparent substrates or devices including charge-coupled devices (CCD), or complementary metal-oxide semiconductor (CMOS) image sensors, light-emitting diodes (LED), a micro-LED (uLED) display, organic light-emitting diode (OLED) or vertical-cavity surface-emitting laser (VCSELs). The optical elements can have interlayers formed in between optical element layers, where the interlayers can range in thickness from 1 nm to 3 mm.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ludovic Godet, Wayne McMillan, Rutger Meyer Timmerman Thijssen, Naamah Argaman, Tapashree Roy, Sage Doshay
  • Patent number: 10700180
    Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, a first gate spacer, an interlayer dielectric layer, a contact stop layer, and an air gap. The gate structure is disposed over the semiconductor substrate. The first gate spacer covers a first sidewall of the gate structure. The interlayer dielectric layer is adjacent to the first gate spacer. The contact stop layer is positioned over the first gate spacer and the interlayer dielectric layer. The air gap is between the first gate spacer and the interlayer dielectric layer. The contact stop layer includes a capping portion that seals a top of the air gap.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10692998
    Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 23, 2020
    Assignee: Cree, Inc.
    Inventors: Khaled Fayed, Simon Wood
  • Patent number: 10692844
    Abstract: A micro-transfer printed intermediate structure comprises an intermediate substrate and one or more pixel structures disposed on the intermediate substrate. Each pixel structure includes an LED, a color filter, and a fractured pixel tether physically attached to the pixel structure. A fractured intermediate tether is physically attached to the intermediate substrate. A method of making an intermediate structure source wafer comprises providing a source wafer having a patterned sacrificial layer including sacrificial portions separated by anchors, disposing an intermediate substrate over the patterned sacrificial layer, and disposing one or more pixel structures on the intermediate substrate entirely on or over each sacrificial portion. Each pixel structure includes an LED, a color filter, and a fractured pixel tether physically attached to the pixel structure to form an intermediate structure.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 23, 2020
    Assignee: X Display Company Technology Limited
    Inventors: Ronald S. Cok, Christopher Andrew Bower
  • Patent number: 10686038
    Abstract: An RC-IGBT includes a semiconductor body incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process and the field stop zone has an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In alternate embodiments, RC-IGBT device, including the epitaxial layer field stop zone, are realized through a fabrication process that uses front side processing only to form the backside contact regions and the front side device region. The fabrication method forms an RC-IGBT device using front side processing to form the backside contact regions and then using wafer bonding process to flip the semiconductor structure onto a carrier wafer so that front side processing is used again to form the device region.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 16, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Hongyong Xue, Lei Zhang, Brian Schorr, Chris Wiebe, Wenjun Li
  • Patent number: 10658353
    Abstract: An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render sufficient protection from ESD events with reduced diode footprint. The bottom diode is serially connected to the top diode via a conductive strap structure.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Tak Ning
  • Patent number: 10651344
    Abstract: A light-emitting device includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a surrounding part surrounding the semiconductor structure and exposing a surface of the first semiconductor layer; a first insulating structure formed on the semiconductor structure, including a plurality of protrusions covering the surface of the first semiconductor layer and a plurality of recesses exposing the surface of the first semiconductor layer; a first contact portion formed on the surrounding part and contacting the surface of the first semiconductor layer by the plurality of recesses; a first pad formed on the semiconductor structure; and a second pad formed on the semiconductor structure.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: May 12, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Wen-Hung Chuang, Cheng-Lin Lu
  • Patent number: 10643870
    Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 5, 2020
    Assignee: eLux Inc.
    Inventors: Paul John Schuele, David Robert Heine, Mark Albert Crowder, Sean Mathew Garner, Changqing Zhan, Avinash Tukaram Shinde, Kenji Alexander Sasaki, Kurt Michael Ulmer
  • Patent number: 10644187
    Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 5, 2020
    Assignee: Artilux, Inc.
    Inventors: Chien-Yu Chen, Szu-Lin Cheng, Chieh-Ting Lin, Yu-Hsuan Liu, Ming-Jay Yang, Shu-Lu Chen, Tsung-Ting Wu, Chia-Peng Lin
  • Patent number: 10636753
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: April 28, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
  • Patent number: 10636878
    Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peter Ramvall, Matthias Passlack
  • Patent number: 10629631
    Abstract: A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode. The drain electrode includes an overlapping portion overlapping with the gate electrode. The gate integrated circuit transmits the scan signals along the scan lines. A size of the overlapping portion increases along a transmitting direction of the scan signal along the scan line.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: April 21, 2020
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventors: Ming-Tsung Wang, Chih-Chung Liu, Yi-Hsiu Cheng, Wen-Qiang Yu
  • Patent number: 10626008
    Abstract: A micro-electro-mechanical device formed in a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region above the first buried cavity; and a second buried cavity extending in the sensitive region. A decoupling trench extends from a first face of the monolithic body as far as the first buried cavity and laterally surrounds the second buried cavity. The decoupling trench separates the sensitive region from a peripheral portion of the monolithic body.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 21, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Lorenzo Baldo, Enri Duqi, Flavio Francesco Villa
  • Patent number: 10622274
    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 14, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
  • Patent number: 10622452
    Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 14, 2020
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
  • Patent number: 10622546
    Abstract: A magnetic memory device includes a substrate, a tunnel barrier pattern on the substrate, a first magnetic pattern and a second magnetic pattern spaced apart from each other with the tunnel barrier pattern therebetween, and a short preventing pattern spaced apart from the tunnel barrier pattern with the second magnetic pattern therebetween. The short preventing pattern includes at least two oxide layers and at least two metal layers, which are alternately stacked.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Chul Lee, Se Chung Oh, Sangjun Yun, Jae Hoon Kim, KyungTae Nam, Eunsun Noh
  • Patent number: 10622441
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor apparatus and manufacturing methods for the same.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 14, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Hai Zhao
  • Patent number: 10615083
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOX) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOX) and removal of the GeOX results in formation of a pure silicon dioxide (SiO2) layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki