Patents Examined by Yosef Gebreyesus
  • Patent number: 10615083
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOX) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOX) and removal of the GeOX results in formation of a pure silicon dioxide (SiO2) layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki
  • Patent number: 10606138
    Abstract: A display substrate repairing method, a display substrate repairing system, a display substrate and a display panel are provided. The display substrate repairing method includes: forming, in the case that a signal line of the display substrate is detected to be open-circuited or short-circuited, a repair line at a disconnected portion of the signal line being open-circuited or a disconnected portion of the signal line formed during a short circuit repairing process; forming a protective layer at least in an area where the repair line is located.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: March 31, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xingfeng Ren, Yaoyao Feng, Yongjiu Cheng
  • Patent number: 10600809
    Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate having a bottom substrate, a buried oxide layer disposed on the bottom substrate, and a semiconductor layer disposed on the buried oxide layer. The semiconductor structure further includes a doped layer embedded in the semiconductor layer and above the buried oxide layer, and a contact structure extending into the semiconductor layer from the top surface of the semiconductor layer. The contact structure is electrically connected to the doped layer.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 24, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung Lee, Chun-Ting Yang, Ho-Chien Chen, Yu-Ting Wei
  • Patent number: 10600800
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Shinsuke Yada, Yanli Zhang
  • Patent number: 10593714
    Abstract: An imaging device includes: a pixel that includes a semiconductor substrate including a first diffusion region containing a first impurity of a first conductivity type, and a second diffusion region containing a second impurity of the first conductivity type, a concentration of the first impurity in the first diffusion region being less than a concentration of the second impurity in the second diffusion region, an area of the first diffusion region being less than an area of the second diffusion region in a plan view, a photoelectric converter configured to convert light into charges, and a first transistor including a source and a drain, the first diffusion region functioning as one of the source and the drain, the second diffusion region functioning as the other of the source and the drain, the first diffusion region being configured to store at least a part of the charges.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 17, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshihiro Sato, Junji Hirase, Yoshinori Takami
  • Patent number: 10593866
    Abstract: Magnetic field assisted magnetoresistive random access memory (MRAM) structures, integrated circuits including MRAM structures, and methods for fabricating integrated circuits including MRAM structures are provided. An exemplary integrated circuit includes a magnetoresistive random access memory (MRAM) structure and a magnetic field assist structure to generate a selected net magnetic field on the MRAM structure.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Chenchen Jacob Wang, Michael Nicolas Albert Tran, Dimitri Houssameddine, Eng Huat Toh
  • Patent number: 10580772
    Abstract: A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10580685
    Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Hong Yu, Laertis Economikos
  • Patent number: 10573636
    Abstract: Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 25, 2020
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Fei Yao, Shijun Wang, Dengping Yin
  • Patent number: 10573715
    Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Harold W. Kennel, Paul B. Fischer, Stephen M. Cea
  • Patent number: 10566248
    Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Ruilong Xie, Chanro Park, Guillaume Bouche
  • Patent number: 10566419
    Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jae Taek Kim
  • Patent number: 10559564
    Abstract: A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10553486
    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Patent number: 10535636
    Abstract: A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen
  • Patent number: 10535754
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, ChoongHyun Lee, Kangguo Cheng, Juntao Li
  • Patent number: 10529886
    Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: January 7, 2020
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Han-Din Liu, Shu-Lu Chen, Yun-Chung Na, Hui-Wen Chen
  • Patent number: 10522719
    Abstract: A micro-transfer color-filter device comprises a color filter, an electrical conductor disposed in contact with the color filter, and at least a portion of a color-filter tether attached to the color filter or structures formed in contact with the color filter. In certain embodiments, a color filter is a variable color filter electrically controlled through one or more electrodes and can be responsive to heat, electrical current, or an electrical field to modify its optical properties, such as color, transparency, absorption, or reflection. In certain embodiments, A color-filter device includes connection posts and can be provided in or on a source wafer suitable for micro-transfer printing. In some embodiments, a color-filter device is disposed on a device substrate and can include a control circuit for controlling the color filter. An array of micro-transfer color-filter devices can be disposed on a display substrate in order to form a display.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 31, 2019
    Assignee: X-Celeprint Limited
    Inventors: Ronald S. Cok, Christopher Andrew Bower, Robert R. Rotzoll, Mark Willner
  • Patent number: 10510645
    Abstract: A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10510620
    Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. A first WFM for one FET is deposited over the first active nanostructure, the pillar and the second active nanostructure. The first WFM is removed from a part of the pillar. The removing creates a discontinuity in the first WFM over the first active nano structure from the first WFM over the second active nanostructure but leaves the first WFM on sidewalls of the pillar. When the first WFM surrounding the second active nanostructure is removed, the pillar and the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. Depositing a second WFM surrounding the second active nanostructure and the isolation pillar forms part of the gate for the second FET and couples the FETs together.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Daniel Chanemougame, Steven R. Soss, Steven J. Bentley, Julien Frougier, Ruilong Xie